Patents by Inventor Alwood P. Williams, III
Alwood P. Williams, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11165766Abstract: A method and computer system for implementing authentication protocol for merging multiple server nodes with trusted platform modules (TPMs) utilizing provisioned node certificates to support concurrent node add and node remove. Each of the multiple server nodes boots an instance of enablement level firmware and extended to a trusted platform module (TPM) on each node as the server nodes are powered up. A hardware secure channel is established between the server nodes for firmware message passing as part of physical configuration of the server nodes to be merged. A shared secret is securely exchanged via the hardware secure channel between the server nodes establishing an initial authentication value shared among all server nodes. All server nodes confirm common security configuration settings and exchange TPM log and platform configuration register (PCR) data to establish common history for future attestation requirements, enabling dynamic changing the server nodes and concurrently adding and removing nodes.Type: GrantFiled: August 21, 2018Date of Patent: November 2, 2021Assignee: International Business Machines CorporationInventors: Timothy R. Block, Elaine R. Palmer, Kenneth A. Goldman, William E. Hall, Hugo M. Krawczyk, David D. Sanner, Christopher J. Engel, Peter A. Sandon, Alwood P. Williams, III
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Publication number: 20200067912Abstract: A method and computer system for implementing authentication protocol for merging multiple server nodes with trusted platform modules (TPMs) utilizing provisioned node certificates to support concurrent node add and node remove. Each of the multiple server nodes boots an instance of enablement level firmware and extended to a trusted platform module (TPM) on each node as the server nodes are powered up. A hardware secure channel is established between the server nodes for firmware message passing as part of physical configuration of the server nodes to be merged. A shared secret is securely exchanged via the hardware secure channel between the server nodes establishing an initial authentication value shared among all server nodes. All server nodes confirm common security configuration settings and exchange TPM log and platform configuration register (PCR) data to establish common history for future attestation requirements, enabling dynamic changing the server nodes and concurrently adding and removing nodes.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Inventors: Timothy R. Block, Elaine R. Palmer, Kenneth A. Goldman, William E. Hall, Hugo M. Krawczyk, David D. Sanner, Christopher J. Engel, Peter A. Sandon, Alwood P. Williams, III
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Patent number: 8578200Abstract: Method, apparatus and system are described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used for converting subsequently received timestamps to a recognized standard. Moreover, the system updates the time base if a counter failure at the external device is detected. When the external device transmits subsequent data, the time base is added to the subsequently received timestamps to convert the subsequent timestamps to a time-recording standard recognized by the computing system.Type: GrantFiled: April 14, 2011Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Aditya Kumar, Kevin Wendzel, Alwood P. Williams, III
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Patent number: 8578201Abstract: Method is described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used for converting subsequently received timestamps to a recognized standard. Moreover, the system updates the time base if a counter failure at the external device is detected. When the external device transmits subsequent data, the time base is added to the subsequently received timestamps to convert the subsequent timestamps to a time-recording standard recognized by the computing system.Type: GrantFiled: November 25, 2012Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Aditya Kumar, Kevin Wendzel, Alwood P. Williams, III
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Patent number: 8447772Abstract: Embodiments of the invention provide a method of optimizing a query, including determining an execution plan for use in executing the query, based on a monetary cost of the energy needed to execute the query. A query optimization component may determine a plurality of execution plans for the query. The query optimization component may then select one of the plans to use in executing the query based on the monetary cost calculated for the plan.Type: GrantFiled: June 23, 2010Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Lynnette E. Carston, Samuel J. Miller, Gary E. Rohret, Jeffrey W. Tenner, Alwood P. Williams, III
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Publication number: 20120266010Abstract: Method, apparatus and system are described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used for converting subsequently received timestamps to a recognized standard. Moreover, the system updates the time base if a counter failure at the external device is detected. When the external device transmits subsequent data, the time base is added to the subsequently received timestamps to convert the subsequent timestamps to a time-recording standard recognized by the computing system.Type: ApplicationFiled: April 14, 2011Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: ADITYA KUMAR, KEVIN WENDZEL, ALWOOD P. WILLIAMS, III
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Patent number: 8195981Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.Type: GrantFiled: June 3, 2008Date of Patent: June 5, 2012Assignee: International Business Machines CorporationInventors: Marc A. Gollub, Zane C. Shelley, Alwood P. Williams, III
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Patent number: 7953914Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.Type: GrantFiled: June 3, 2008Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Marc A. Gollub, Zane C. Shelley, Alwood P. Williams, III
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Patent number: 7895477Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.Type: GrantFiled: June 3, 2008Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Marc A. Gollub, Zane C. Shelley, Alwood P. Williams, III
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Patent number: 7698601Abstract: A minimally degraded configuration is determined when failing connections occur. Associative deconfigurations are determined from deconfiguring hardware items in a server system, associative groups are derived, and failed connections are determined. Failed connections are determined between two hardware items that are in the same associative group, and the two hardware items at both endpoints of the failed connection are deconfigured. Each associative group state is set to unknown, and the failed connections are counted where a single endpoint of the failed connection is within the associative group. The associative group state is set to deconfigured, if a member of the associative group was deconfigured. Counts of the associative groups that remain in the unknown state are analyzed, and the associative group with the smallest failed connection count is selected and set to a configured state.Type: GrantFiled: July 13, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Sheldon R. Bailey, Alwood P. Williams, III
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Publication number: 20090300290Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.Type: ApplicationFiled: June 3, 2008Publication date: December 3, 2009Inventors: Marc A. Gollub, Zane C. Shelley, Alwood P. Williams, III
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Publication number: 20090300434Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.Type: ApplicationFiled: June 3, 2008Publication date: December 3, 2009Inventors: Marc A. Gollub, Zane C. Shelley, Alwood P. Williams, III
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Publication number: 20090300425Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.Type: ApplicationFiled: June 3, 2008Publication date: December 3, 2009Inventors: Marc A. Gollub, Zane C. Shelley, Alwood P. Williams, III
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Patent number: 7502953Abstract: A method for coupling a collection of master devices on an Inter-Integrated Circuit (IIC) bus, where the collection of master devices includes at least one resident master device, generating a periodic, fixed interval tenure on the IIC bus, synchronizing at least one additional master device with the periodic, fixed interval tenure to enable the at least one additional master device to communicate on the IIC bus, and tuning a period value corresponding to a frequency of the periodic, fixed interval tenure to optimize the synchronizing, wherein the tuning further includes adjusting the period value to vary the frequency of the periodic, fixed interval tenure to balance between available IIC bus bandwidth and synchronization of the at least one additional master device.Type: GrantFiled: January 5, 2006Date of Patent: March 10, 2009Assignee: International Business Machines CorporationInventors: Douglas M. Boecker, Nathan D. Miller, Alwood P. Williams, III
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Publication number: 20090019309Abstract: A minimally degraded configuration is determined when failing connections occur. Associative deconfigurations are determined from deconfiguring hardware items in a server system, associative groups are derived, and failed connections are determined. Failed connections are determined between two hardware items that are in the same associative group, and the two hardware items at both endpoints of the failed connection are deconfigured. Each associative group state is set to unknown, and the failed connections are counted where a single endpoint of the failed connection is within the associative group. The associative group state is set to deconfigured, if a member of the associative group was deconfigured. Counts of the associative groups that remain in the unknown state are analyzed, and the associative group with the smallest failed connection count is selected and set to a configured state.Type: ApplicationFiled: July 13, 2007Publication date: January 15, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sheldon R. Bailey, Alwood P. Williams, III