Patents by Inventor Alwood Patrick Williams, III
Alwood Patrick Williams, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10949321Abstract: Operational management of an integrated circuit device can be performed by a microcontroller based on information associated with the notification messages generated by the integrated circuit device. The notification messages may include timestamps and metadata for different notification types which can be used to build a timeline. The microcontroller may use the information to monitor the operational health and performance of the integrated circuit device or can communicate this information to a remote management server.Type: GrantFiled: November 26, 2018Date of Patent: March 16, 2021Assignee: Amazon Technologies, Inc.Inventors: Thomas A. Volpe, Alwood Patrick Williams, III, Brian Robert Silver
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Patent number: 9250920Abstract: A method for initializing processor cores in a multiprocessor system. The method includes a microcontroller initializing a first processor utilizing a common initialization image for all processor cores within the first processor. The first processor detects and executes system firmware. All remaining processors are initialized utilizing the common initialization image. The executing firmware detects a system configuration of the multiprocessor system. A customized processor initialization image for each of the processor cores in the multiprocessor system is generated and stored to a storage device. The processor cores are triggered to enter a power save state in which all initialization settings of the processor cores are lost. In response to all the processor cores entering the power save state, the first processor core of the first processor is re-initialized using a first customized initialization image generated for the first processor core.Type: GrantFiled: February 28, 2013Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: David Dean Sanner, III, Jeshua Daniel Smith, Gregory Scott Still, Alwood Patrick Williams, III
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Patent number: 9229729Abstract: A system and computer program product for initializing processor cores in a multiprocessor system. The system includes a microcontroller that initializes a first processor utilizing a common initialization image for all processor cores within the first processor. The first processor detects and executes system firmware. All remaining processors are initialized utilizing the common initialization image. The executing firmware detects a system configuration of the multiprocessor system. A customized processor initialization image for each of the processor cores in the multiprocessor system is generated and stored to a storage device. The processor cores are triggered to enter a power save state in which all initialization settings of the processor cores are lost. In response to all the processor cores entering the power save state, the first processor core of the first processor is re-initialized using a first customized initialization image generated for the first processor core.Type: GrantFiled: November 26, 2012Date of Patent: January 5, 2016Assignee: International Business Machines CorporationInventors: David Dean Sanner, III, Jeshua Daniel Smith, Gregory Scott Still, Alwood Patrick Williams, III
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Publication number: 20140149732Abstract: A method for initializing processor cores in a multiprocessor system. The method includes a microcontroller initializing a first processor utilizing a common initialization image for all processor cores within the first processor. The first processor detects and executes system firmware. All remaining processors are initialized utilizing the common initialization image. The executing firmware detects a system configuration of the multiprocessor system. A customized processor initialization image for each of the processor cores in the multiprocessor system is generated and stored to a storage device. The processor cores are triggered to enter a power save state in which all initialization settings of the processor cores are lost. In response to all the processor cores entering the power save state, the first processor core of the first processor is re-initialized using a first customized initialization image generated for the first processor core.Type: ApplicationFiled: February 28, 2013Publication date: May 29, 2014Inventors: DAVID DEAN SANNER, III, JESHUA DANIEL SMITH, GREGORY SCOTT STILL, ALWOOD PATRICK WILLIAMS, III
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Publication number: 20140149727Abstract: A system and computer program product for initializing processor cores in a multiprocessor system. The system includes a microcontroller that initializes a first processor utilizing a common initialization image for all processor cores within the first processor. The first processor detects and executes system firmware. All remaining processors are initialized utilizing the common initialization image. The executing firmware detects a system configuration of the multiprocessor system. A customized processor initialization image for each of the processor cores in the multiprocessor system is generated and stored to a storage device. The processor cores are triggered to enter a power save state in which all initialization settings of the processor cores are lost. In response to all the processor cores entering the power save state, the first processor core of the first processor is re-initialized using a first customized initialization image generated for the first processor core.Type: ApplicationFiled: November 26, 2012Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: DAVID DEAN SANNER, III, JESHUA DANIEL SMITH, GREGORY SCOTT STILL, ALWOOD PATRICK WILLIAMS, III
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Patent number: 8510714Abstract: A method, apparatus, and computer program product to implement integrated documentation and functional application testing are provided. An integrated test engine drives both functional application testing and documentation testing for the application. The integrated test engine uses documentation instructions, which are embedded with metadata and represent how to automate each step in the documentation and the expected results, and runs a series of tests that ensure that the application works as expected and that the documentation accurately reflects how the application works.Type: GrantFiled: April 16, 2009Date of Patent: August 13, 2013Assignee: International Business Machines CorporationInventors: Amber Rebecca Field King, John Peter Merges, III, Diane Elaine Olson, Alwood Patrick Williams, III
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Patent number: 7895493Abstract: A method, apparatus and program product improve computer reliability by, in part, identifying a plurality of error occurrences from Error Correction Codes. It may then be determined if the plurality of error occurrences are associated with a single bit of a bus. The determined, single bit may correspond to a faulty component of the bus. This level of identification efficiently addresses problems. For instance, a corrective algorithm may be applied if the plurality of error occurrences are associated with the single bit. Alternatively, the bus may be disabled if the plurality of error occurrences are not associated with the single bit of the bus. In this manner, implementations may detect, identify and act in response to multiple failure modes.Type: GrantFiled: April 28, 2008Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Wayne Lemmon, Zane Coy Shelley, Alwood Patrick Williams, III
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Patent number: 7886088Abstract: A mechanism is provided for locking an end device for the period of time that the device is needed, thus disabling access by any other application or process. Having the device locked, rather than the bus, allows other applications to use the bus to access other devices at the same time. This is achieved by providing a virtual bus arbitration, which arbitrates applications' use of the physical bus. The virtual bus arbitration algorithms allow bus operations from different applications to overlap on the physical bus as long as their target devices and associated bus locks are on different end devices.Type: GrantFiled: March 18, 2008Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventors: Douglas Michael Boecker, Stephan Otis Broyles, Hemlata Nellimarla, Alwood Patrick Williams, III
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Publication number: 20100269100Abstract: A method, apparatus, and computer program product to implement integrated documentation and functional application testing are provided. An integrated test engine drives both functional application testing and documentation testing for the application. The integrated test engine uses documentation instructions, which are embedded with metadata and represent how to automate each step in the documentation and the expected results, and runs a series of tests that ensure that the application works as expected and that the documentation accurately reflects how the application works.Type: ApplicationFiled: April 16, 2009Publication date: October 21, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Amber Rebecca Field King, John Peter Merges, III, Diane Elaine Olson, Alwood Patrick Williams, III
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Publication number: 20090271668Abstract: A method, apparatus and program product improve computer reliability by, in part, identifying a plurality of error occurrences from Error Correction Codes. It may then be determined if the plurality of error occurrences are associated with a single bit of a bus. The determined, single bit may correspond to a faulty component of the bus. This level of identification efficiently addresses problems. For instance, a corrective algorithm may be applied if the plurality of error occurrences are associated with the single bit. Alternatively, the bus may be disabled if the plurality of error occurrences are not associated with the single bit of the bus. In this manner, implementations may detect, identify and act in response to multiple failure modes.Type: ApplicationFiled: April 28, 2008Publication date: October 29, 2009Inventors: Wayne Lemmon, Zane Coy Shelley, Alwood Patrick Williams, III
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Patent number: 7383364Abstract: A mechanism is provided for locking an end device for the period of time that the device is needed, thus disabling access by any other application or process. Having the device locked, rather than the bus, allows other applications to use the bus to access other devices at the same time. This is achieved by providing a virtual bus arbitration, which arbitrates applications' use of the physical bus. The virtual bus arbitration algorithms allow bus operations from different applications to overlap on the physical bus as long as their target devices and associated bus locks are on different end devices.Type: GrantFiled: July 31, 2003Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventors: Douglas Michael Boecker, Stephan Otis Broyles, Hemlata Nellimarla, Alwood Patrick Williams, III