Patents by Inventor Alyssa N. Scarbrough

Alyssa N. Scarbrough has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220246628
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Simultaneously, (a), (b), and (c) are formed, where (a): horizontally-elongated trenches into the stack laterally-between immediately-laterally-adjacent of the memory-block regions; (b): channel openings into the stack laterally-between the horizontally-elongated trenches; and (c): through-array-via (TAV) openings into the stack in a stair-step region. Intervening material is formed in the horizontally-elongated trenches, a channel-material string in individual of the channel openings, and conductive material in the TAV openings. Other aspects, including structure independent of method, are disclosed.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, John D. Hopkins
  • Publication number: 20220246536
    Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the first memory region, the intermediate region and the second memory region. The panel is between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the first memory region, the second memory region and the intermediate region, and is directly adjacent the panel. The doped-semiconductor-material is at least part of conductive source structures within the first and second memory regions. Insulative rings surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Alyssa N. Scarbrough, Jordan D. Greenlee
  • Publication number: 20220246634
    Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and the other region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. The doped-semiconductor-material is at least part of the source structure within the memory region. Liners are directly adjacent to the conductive posts and laterally surround the conductive posts. The liners are between the conductive posts and the doped-semiconductor-material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, Jordan D. Greenlee, John D. Hopkins
  • Publication number: 20220246635
    Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the memory regions and the intermediate region. The panel is laterally between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the memory regions and the intermediate region, and is directly adjacent to the panel. The doped-semiconductor-material is at least part of conductive source structures within the memory regions. Insulative rings laterally surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Insulative liners are along upper regions of the conductive posts. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: February 1, 2021
    Publication date: August 4, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, John D. Hopkins, Jordan D. Greenlee
  • Patent number: 11398427
    Abstract: Some embodiments include a method in which a first stack of alternating first and second levels is formed. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels and one of the first levels. An etch-stop material and a liner are formed over the stack. A first material is formed over the etch-stop material. Openings are formed to extend through the first material to the etch-stop material. Sacrificial material is formed within the openings. A second stack is formed over the first stack. A second material is formed over the first material. Conductive layers are formed within the first levels. Additional openings are formed to extend to the sacrificial material, and are then extended through the sacrificial material to the conductive layers within the steps. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, John D. Hopkins
  • Publication number: 20220165742
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions, Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally therealong in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion.
    Type: Application
    Filed: February 14, 2022
    Publication date: May 26, 2022
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Alyssa N. Scarbrough
  • Publication number: 20220149066
    Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material in a lowest of the conductive tiers comprises intervenor material. Bridges extend laterally-between the immediately-laterally-adjacent memory blocks. The bridges comprise bridging material that is of different composition from that of the intervenor material. The bridges are longitudinally-spaced-along the immediately-laterally-adjacent memory blocks by the intervenor material and extend laterally into the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Jordan D. Greenlee, Nancy M. Lomeli, Alyssa N. Scarbrough
  • Publication number: 20220149067
    Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Dummy pillars extend through the insulative tiers and the conductive tiers. A lowest of the conductive tiers comprises conducting material and dummy-region material that is aside and of different composition from that of the conducting material. The channel-material strings extend through the conducting material of the lowest conductive tier. The dummy pillars extend through the dummy-region material of the lowest conductive tier. Other embodiments, including method, are disclosed.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Jordan D. Greenlee, Nancy M. Lomeli, Alyssa N. Scarbrough
  • Patent number: 11282847
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally there-along in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Alyssa N. Scarbrough
  • Publication number: 20220068944
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel openings extend through the first tiers and the second tiers in the memory-block regions. Channel material of channel-material strings is formed in the channel openings and the channel material is formed in the horizontally-elongated trenches. The channel material is removed from the horizontally-elongated trenches and the channel material of the channel-material strings is left in the channel openings. After removing the channel material from the horizontally-elongated trenches, intervening material is formed in the horizontally-elongated trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Alyssa N. Scarbrough
  • Publication number: 20220068958
    Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks that individually comprise a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises alternating first insulating tiers and second insulating tiers. The lower portion comprises a lowest insulator tier directly above conductor material of a conductor tier. The lowest insulator tier comprises solid carbon and nitrogen-containing material. An immediately-adjacent tier is directly above the solid carbon and nitrogen-containing material of the lowest insulator tier.
    Type: Application
    Filed: September 24, 2020
    Publication date: March 3, 2022
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Alyssa N. Scarbrough
  • Publication number: 20220068800
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A lower portion of a stack is formed, with the stack ultimately comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises conductive first sacrificial material. Conductive second material is directly electrically coupled to the conductive first sacrificial material. The conductive first sacrificial material and the conductive second material have different reduction potentials that are at least 0.5V away from one another. A lowest of the second tiers is insulative and below the lowest first tier. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion.
    Type: Application
    Filed: October 14, 2020
    Publication date: March 3, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Collin Howder, John D. Hopkins, Alyssa N. Scarbrough
  • Publication number: 20210372785
    Abstract: Embodiments of the disclosure are drawn to projecting light on a surface and analyzing the scattered light to obtain spatial information of the surface and generate a three dimensional model of the surface. The three dimensional model may then be analyzed to calculate one or more surface characteristics, such as roughness. The surface characteristics may then be analyzed to provide a result, such as a diagnosis or a product recommendation. In some examples, a mobile device is used to analyze the surface.
    Type: Application
    Filed: June 2, 2020
    Publication date: December 2, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Zahra Hosseinimakarem, Jonathan D. Harms, Alyssa N. Scarbrough, Dmitry Vengertsev, Yi Hu
  • Publication number: 20210358843
    Abstract: Some embodiments include a method in which a first stack of alternating first and second levels is formed. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels and one of the first levels. An etch-stop material and a liner are formed over the stack. A first material is formed over the etch-stop material. Openings are formed to extend through the first material to the etch-stop material. Sacrificial material is formed within the openings. A second stack is formed over the first stack. A second material is formed over the first material. Conductive layers are formed within the first levels. Additional openings are formed to extend to the sacrificial material, and are then extended through the sacrificial material to the conductive layers within the steps. Some embodiments include integrated assemblies.
    Type: Application
    Filed: May 12, 2020
    Publication date: November 18, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, John D. Hopkins
  • Publication number: 20210358929
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally there-along in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion.
    Type: Application
    Filed: May 13, 2020
    Publication date: November 18, 2021
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Alyssa N. Scarbrough
  • Patent number: 11094595
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Sacrificial material is formed in the trenches. Vertical recesses are formed in the sacrificial material. The vertical recesses extend across the trenches laterally-between and are longitudinally-spaced-along immediately-laterally-adjacent of the memory-block regions. Bridge material is formed in the vertical recesses to line and less-than-fill the vertical recesses and form bridges there-from that have an upwardly-open cup-like shape. The sacrificial material in the trenches is replaced with intervening material that is directly under the bridges. Additional methods and structures independent of methods are disclosed.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, John D. Hopkins
  • Publication number: 20210202324
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Sacrificial material is formed in the trenches. Vertical recesses are formed in the sacrificial material. The vertical recesses extend across the trenches laterally-between and are longitudinally-spaced-along immediately-laterally-adjacent of the memory-block regions. Bridge material is formed in the vertical recesses to line and less-than-fill the vertical recesses and form bridges there-from that have an upwardly-open cup-like shape. The sacrificial material in the trenches is replaced with intervening material that is directly under the bridges. Additional methods and structures independent of methods are disclosed.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, John D. Hopkins