Abstract: A power on reset circuit continuously asserts a reset output signal to a reset logic state (e.g., RESET) during the recovery of a power supply voltage from an inoperative voltage level, e.g., zero volts, to an operative minimum voltage level. The reset circuit continues to assert the reset output to the reset Logic State for an additional, active reset interval after the power supply voltage is above the minimum operative level. At the end of the additional active reset interval, the reset output is released to an operational logic level (e.g, NOT-RESET or RESET\). Operative logic circuits receiving the reset output signal are thus provided with the active reset interval in which to perform their built-in reset functions after the power supply level is at or above the minimum operative level. At the expiration of the active reset interval, the power on reset circuit provides the subsequent operative circuits with the NON-RESET logic state to indicate normal operation can be resumed.

Abstract: An apparatus for monitoring a thermal state of a system includes a thermal management integrated circuit (IC). The thermal management IC is coupled to receive a remote temperature signal. The remote temperature signal is indicative of a system temperature. The thermal management IC includes a software programmable temperature threshold setpoint, and a hardware programmable temperature critical threshold setpoint.

Abstract: A charge pump circuit including two transfer capacitors, two reservoir capacitors and a plurality of switches. The transfer capacitors are charged to Vin when the charge pump circuit is in a first operating state, the transfer capacitors are connected in a first series arrangement to apply a +2 Vin charge to one of the reservoir capacitors when the charge pump circuit is in a second operating state, and the transfer capacitors are connected in a second series arrangement to apply a -2 Vin charge to the other of the reservoir capacitors when the charge pump circuit is in a third operating state. A control circuit is provided to control the plurality of switches such that the charge pump circuit enters the first through third operating states is a predetermined sequence.

Abstract: A capacitance measuring device incorporates the integrating analog-digital converter circuit of a handheld meter. The capacitance measuring device charges an unknown capacitance with a constant current until the voltage across the unknown capacitor reaches a predetermined voltage. At the same time, a reference voltage is applied to the input lead of an integrating circuit of the integrating analog-digital converter such that a corresponding proportional charge is stored in the feedback capacitor of the integrating circuit. The negative of the reference voltage is then applied to the integrating circuit so that charge is removed from the feedback capacitor at the same rate as the feedback capacitor was charged. A counter is used to determine the number of clock pulses it took to completely discharge the feedback capacitor and hence a reading of the unknown capacitance can be determined from the equation C.sub.X =I.sub.CHARGE *T.sub.2 /V.sub.TRIP.