Patents by Inventor Aman A. Kokrady
Aman A. Kokrady has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9158683Abstract: A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks. An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal. Simultaneous read and write operations are possible.Type: GrantFiled: August 9, 2012Date of Patent: October 13, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Aman A Kokrady, Shahid Ali, Vish Visvanathan, Vinod Joseph Menezes
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Patent number: 9021320Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains.Type: GrantFiled: December 10, 2012Date of Patent: April 28, 2015Assignee: Texas Instruments IncorporatedInventors: Raguram Damodaran, Naveen Bhoria, Aman Kokrady
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Patent number: 9009550Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.Type: GrantFiled: December 10, 2012Date of Patent: April 14, 2015Assignee: Texas Instruments IncorporatedInventors: Raguram Damodaran, Naveen Bhoria, Aman Kokrady
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Patent number: 8977915Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.Type: GrantFiled: December 10, 2012Date of Patent: March 10, 2015Assignee: Texas Instruments IncorporatedInventors: Raguram Damodaran, Naveen Bhoria, Aman Kokrady
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Patent number: 8930783Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.Type: GrantFiled: December 10, 2012Date of Patent: January 6, 2015Assignee: Texas Instruments IncorporatedInventors: Raguram Damodaran, Naveen Bhoria, Aman Kokrady
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Patent number: 8874876Abstract: A method for performing packet lookups is provided. Packets (which each have a body and a header) are received and parsed to parsing headers. A hash function is applied to each header, and each hashed header is compared with a plurality of binary rules stored within a primary table, where each binary rule is a binary version of at least one ternary rule from a first set of ternary rules. For each match failure with the plurality of rules, a secondary table is searched using the header associated with each match failure, where the secondary table includes a second set of ternary rules.Type: GrantFiled: December 12, 2011Date of Patent: October 28, 2014Assignee: Texas Instruments IncorporatedInventors: Sandeep Bhadra, Aman A. Kokrady, Patrick W. Bosshart, Hun-Seok Kim
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Publication number: 20140164844Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.Type: ApplicationFiled: December 10, 2012Publication date: June 12, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Raguram Damodaran, Naveen Bhoria, Aman Kokrady
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Publication number: 20140164855Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.Type: ApplicationFiled: December 10, 2012Publication date: June 12, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Raguram Damodaran, Naveen Bhoria, Aman Kokrady
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Publication number: 20140164854Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains.Type: ApplicationFiled: December 10, 2012Publication date: June 12, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Raguram Damodaran, Naveen Bhoria, Aman Kokrady
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Publication number: 20140164856Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.Type: ApplicationFiled: December 10, 2012Publication date: June 12, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Raguram Damodaran, Naveen Bhoria, Aman Kokrady
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Publication number: 20140047197Abstract: A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks. An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal. Simultaneous read and write operations are possible.Type: ApplicationFiled: August 9, 2012Publication date: February 13, 2014Applicant: TEXAS INSTRUMENTS, INCORPORATEDInventors: Aman A. Kokrady, Shahid Ali, Vish Visvanathan, Vinod Joseph Menezes
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Publication number: 20120246400Abstract: A method for performing packet lookups is provided. Packets (which each have a body and a header) are received and parsed to parsing headers. A hash function is applied to each header, and each hashed header is compared with a plurality of binary rules stored within a primary table, where each binary rule is a binary version of at least one ternary rule from a first set of ternary rules. For each match failure with the plurality of rules, a secondary table is searched using the header associated with each match failure, where the secondary table includes a second set of ternary rules.Type: ApplicationFiled: December 12, 2011Publication date: September 27, 2012Applicant: Texas Instruments IncorporatedInventors: Sandeep Bhadra, Aman A. Kokrady, Patrick W. Bosshart, Hun-Seok Kim