Abstract: The disclosure relates to duty cycle correction of digital data in a CML transmission system. Example embodiments include a CML transmission system (600) comprising: a transmission channel (601) with a transmitter (602) connected to a first end (604) and a receiver (603) connected to a second end (605). A control system (606) is configured to measure a duty cycle of a received signal from the receiver (603) and provide first and second termination resistance control signals (RSTP, RSTN) to respective first and second adjustable receiver termination resistances (501, 502) of the receiver (603) to adjust a balance of the termination resistance control signals (RSTP, RSTN) dependent on a comparison between the measured duty cycle and a nominal duty cycle.

Abstract: A circuit that includes a level shifter. The level shifter includes a shift path with two transistors coupled in series. The circuit also includes a GIDL detection circuit for detecting GIDL current conditions. The GIDL detection circuit generates a GIDL signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a transistor of the shift path to increase the conductivity of the transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least a portion of the shift path when the second transistor is nonconductive due to the level shifter being in a low power mode.

Abstract: A circuit that includes a level shifter. The level shifter includes a shift path with two transistors coupled in series. The circuit also includes a GIDL detection circuit for detecting GIDL current conditions. The GIDL detection circuit generates a GIDL signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a transistor of the shift path to increase the conductivity of the transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least a portion of the shift path when the second transistor is nonconductive due to the level shifter being in a low power mode.