Abstract: An example may, at a first device, input an entity embedding for an entity and an item embedding for a plurality of items to a scoring function. The entity embedding and the item embedding are pre-computed using a first language model. At the first device, a retrieval score for the entity and a first item of the plurality of items is computed. The retrieval score is used to identify an item subset of the plurality of items. A ranking prompt is input to a second language model. The second language model and the first language model have a common parameter value. The second language model generates a ranking score for the entity and a second item in response to the ranking prompt. An online system uses the ranking score to include or exclude the second item from a presentation of digital content to the entity via a device.

Abstract: An example may train a cross encoder embedding model using a ranking instruction, a combined input, a pseudo label, and a combined loss. The combined loss includes a ranking loss and a first retrieval loss. A first entity embedding of an entity and a first item embedding of an item may be obtained from the trained cross encoder embedding model. A first input including the first entity embedding obtained from the trained cross encoder embedding model, a second input including the first item embedding obtained from the trained cross encoder embedding model, and a second retrieval loss, may be used to train a dual encoder retrieval model to produce a trained dual encoder retrieval model. A system may use output of the trained dual encoder retrieval model to include or exclude items from a presentation of digital content items to the entity via a device.

Abstract: Embodiments herein describe a memory controller (MC) in a first integrated circuit (IC) that connect to circuitry in the same integrated circuit (e.g., horizontal direction) and to circuitry in a second IC in the vertical direction. That is, the first and second ICs can be stacked on each other where the MC in the first IC provides an interface for both circuitry in the first IC as well as circuitry in the second IC to communicate with a separate memory device. Thus, the MC includes data paths in both the X direction (e.g., within the same IC) and the Y direction (e.g., to an external IC). In this manner, the MC can provide an interface for circuitry in multiple ICs (or dies or chiplets) to the same external memory device.

Abstract: Techniques for network-on-chip (NoC) memory addressable encryption and authentication. In an embodiment, NoC circuitry includes NoC routing circuitry, memory circuitry that stores a security parameter, and security circuitry that secures (e.g., encrypts and/or authenticates) a payload based on the security parameter. The security circuitry may secure the payload before the payload is packetized for transmission through the NoC, after the payload is de-packetized for output to an endpoint, or as the payload transits the NoC. The security circuitry may be centralized or distributed amongst access points of the NoC. Distributed security circuitry may exchange a security parameter over a secure link of the NoC circuitry. The security circuitry may include decryption circuitry that decrypts a response from a first endpoint before the response is packetized for transmission through the NoC, after the response is de-packetized for output to a second endpoint, or as the response transits the NoC.

Abstract: An example formulates a training input for a neural network model with attention to include action data and descriptive content. The action data includes a first entity identifier (ID) and a first sequence of actions associated with the first entity ID. The descriptive content describes a first entity associated with the first entity ID. An action in the first sequence of actions includes an electronic transmission involving the first entity and a second entity. An example uses the training input, including the first entity ID, and a non-standardized tokenizer, to train the neural network model with attention to generate and output a second sequence of actions.

Abstract: A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.

Abstract: System and method for automated filter determination of Sigma rules used in a malicious content detection system is provided. The system and method can include training a machine learning algorithm based on candidate sets that can be determined based on a plurality of sigma rules, and performing inference for a plurality candidate sets corresponding to a plurality of sigma rules based on the machine learning algorithm to detect malicious content.

Abstract: A circuit arrangement includes a plurality of cryptographic accelerators. Each cryptographic accelerator is configured to perform cryptographic operations according to a respective cryptographic protocol. A first memory is coupled to the cryptographic accelerators. A first processor is configured to specify, in response to requests to perform the cryptographic operations, parameters to the cryptographic accelerators according to the requests. The first processor is configured to identify, in the first memory, keys that are associated with the cryptographic accelerators, and signal the cryptographic accelerators to commence performing the cryptographic operations according to the parameters and using the associated keys.

Abstract: Techniques for authenticating user access to a resource and providing access to the resource include non-transitory computer-readable media storing program instructions that, when executed by one or more processors associated with a first computing device, cause the one or more processors to perform a method including receiving, from a client device, a first request for an authentication token to access a resource and identifying a second computing device through which the resource is accessible. The method further includes transmitting a second request to the second computing device for the authentication token, receiving a signed authentication token from the second computing device, wherein the authentication token is signed by the second computing device and specific to the client device, and providing the signed authentication token to the client device.

Abstract: A memory device includes a memory array with a plurality of memory cells formed at respective intersections of a plurality of wordlines and a plurality of bit lines. The memory device further control logic to initiate a program operation on one or more memory cells in a first block of the memory array, the program operation comprising a program phase, a program recovery phase, and a program exit phase. The control logic further causes a positive voltage pulse having a fixed duration to be applied to at least a subset of a plurality of bitlines of the memory array during the program exit phase of the program operation and causes the positive voltage pulse having the fixed duration to be applied to an access line controlling one or more drain-side select gate devices in the first block of the memory array during the program exit phase of the program operation.

Abstract: Methods, systems, and apparatuses include receiving an event notification for an event associated with a node of a graph network. Event data including node state data and a timestamp is generated using the event notification. A node state change is generated for the node by applying a neural network to the node state data and the timestamp. An input sequence for a generative machine learning model is generated, the input sequence including the node state change and the node state data. Updated node state data is computed for the node by applying the generative machine learning model to the input sequence. A node encoding is generated for the node using the updated node state data. Input data for a trained machine learning model is generated using the node encoding. An output of the trained machine learning model is generated by applying the trained machine learning model to the input data.

Abstract: In described examples, an integrated circuit (IC) includes a differential to single ended (DSE) circuit, and first, second, third, and fourth transistors. A control terminal of the first transistor is coupled to a first output of the DSE circuit. A control terminal of the second transistor is coupled to a second output of the DSE circuit. A first terminal of the third transistor is coupled to a first terminal of the first transistor and a control terminal of the third transistor is coupled to a first terminal of the second transistor. A first terminal of the fourth transistor is coupled to the first terminal of the second transistor, and a control terminal of the fourth transistor is coupled to the first terminal of the first transistor.

Abstract: Methods, systems, and devices for techniques for word line group (WLG) dependent read recovery (RRCV) period ramp down comprise initiating a read recovery process associated with a block of the array of memory cells, where the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; and causing the second group of word lines to be ramped from the initial voltage to a second ramp-down voltage, where the second ramp-down voltage is greater than a first ramp-down voltage for the first group of word lines. The second group of word lines may comprise an edge group of word lines within the block of the array of memory cells. The first ramp-down voltage may be a ground voltage or a negative voltage, and the second ramp-down voltage may be a voltage greater than the ground voltage.

Abstract: Embodiments of the disclosed technologies are capable of generating, using a machine learning model and a prompt, first content recommendations. The prompt comprises a search query and historic information associated with an entity. The first content recommendations are presented. The embodiments describe receiving a selection of a content recommendation of the first content recommendations. The embodiments describe generating, using the machine learning model and a second prompt, second content recommendations. The second prompt comprises a second search query and second historic information associated with the entity. The embodiments describe generating a ranked order of the second content recommendations using a history of entity interactions including the selection of the content recommendation of the first content recommendations. The embodiments describe determining context-aware recommendations by optimizing a permutation of the ranked order of the second content recommendations.

Abstract: System and method for automated filter determination of Sigma rules used in a malicious content detection system is provided. The system and method can include training a machine learning algorithm based on candidate sets that can be determined based on a plurality of sigma rules, and performing inference for a plurality candidate sets corresponding to a plurality of sigma rules based on the machine learning algorithm to detect malicious content.

Abstract: A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.

Abstract: Aspects of the disclosure include methods for leveraging retrieval augmented generation (RAG) over a graph neural network (GNN) for edge building and the generation of reason-aware graph recommendations. A method can include constructing a graph neural network from an input graph having a plurality of nodes and one or more edges. The graph neural network includes one or more internal layers, each internal layer having one or more node vectors encoding a K-hop neighborhood for a target node of the plurality of nodes. RAG data including non-graph contextual data is retrieved for each of the plurality of nodes and transformed into embeddings using a large language model encoder. The RAG embeddings are encoded into node vectors of the graph neural network. The graph neural network generates a representation for the target node that is transformed by a feed forward neural network tower into an output vector.

Abstract: An integrated circuit device includes a processing element, a plurality of memory controllers, and a network on chip (NoC). The NoC has a first network including a plurality of interconnected switches having routing tables and a second network coupled to the first network. The second network includes a crossbar. The NoC is configured to implement a path coupling the processing element and the plurality of memory controllers in which a first portion of the path is implemented in the first network and a second portion of the path is implemented in the second network. The crossbar connects the processing element to any memory controller of the plurality of memory controllers while maintaining a same delay for the path.

Abstract: Embodiments herein describe techniques to extend a network-on-chip (NoC) across multiple IC dice in 3D. An integrated circuit (IC) device includes first and second vertically-stacked IC dice, and an inter-die bus that interfaces between the second die and a NoC packet switch (NPS) of the first die. The inter-die bus may include one or more driver circuits coupled to inter-die links of the inter-die bus. Communications over the inter-die links may be synchronous (e.g., packet-based) or asynchronous with the NPS (e.g., based on a point-to-point protocol, such as an AXI protocol). The inter-die bus may interface with a circuit block of the second IC device via a point-to-point (e.g., AXI) protocol or via a NPS of the second IC die. The IC device may include multiple inter-die buses, which may expand inter-die and intra-die routing options.

Abstract: A system includes a plurality of processing elements and a plurality of memory controllers. The system includes a network on chip (NoC) providing connectivity between the plurality of processing elements and the plurality of memory controllers. The NoC includes a sparse network coupled to the plurality of processing elements and a non-blocking network coupled to the sparse network and the plurality of memory controllers. The plurality of processing elements execute a plurality of applications. Each application has a same deterministic memory access performance in accessing associated ones of the plurality of memory controllers via the sparse network and the non-blocking network of the NoC.