Patents by Inventor Aman Gupta
Aman Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240144210Abstract: A method for optimizing invoice payments according to supplier and buyer controls includes: receiving one or more received data message including invoice data, a buyer identification value, a supplier identification value, and a plurality of buyer optimization priorities, wherein the invoice data is associated with an invoice and includes an invoice amount and due date; identifying a plurality of supplier controls associated with the supplier identification value; identifying one or more buyer preferences associated with the buyer identification value; determining an optimal payment schedule for one or more payment transactions for the invoice based on the invoice data, the buyer optimization priorities, the plurality of supplier controls, and the one or more buyer preferences; transmitting a transmitted data message including the determined optimal payment schedule.Type: ApplicationFiled: October 26, 2022Publication date: May 2, 2024Inventors: Srinivasan CHANDRASEKHARAN, Ganesh Nagendra PRASAD, Ross HARRIS, Alonso ARAUJO, Anubha PANDEY, Deepak BHATT, Aman GUPTA, Tanmoy BHOWMIK
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Patent number: 11961115Abstract: In some examples, a computing device may receive data from a plurality of groups of data sources. The computing device may access a plurality of data synthetization machine learning models configured for generating synthetic data. Respective ones of the data synthetization machine learning models may correspond to respective ones of the groups of data sources. The computing device generates first synthetic data by inputting, to a first data synthetization machine learning model, first data received from a first data source group, and generates second synthetic data by inputting, to a second data synthetization machine learning model, second data received from a second data source group. The computing device determines an allocation of resources based at least in part on comparing the first data and the first synthetic data with the second data and the second synthetic data.Type: GrantFiled: May 18, 2023Date of Patent: April 16, 2024Assignee: DOORDASH, INC.Inventors: Robert Bryant Kaspar, Alok Gupta, Aman Dhesi
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Publication number: 20240089136Abstract: Methods, computer systems, and computer-storage media, and graphical user interfaces are provided for facilitating efficient meeting management, according to embodiments of the present technology. In one embodiment, engagement data associated with an attendee of an online meeting is obtained. Thereafter, an engagement metric is generated using the engagement data, the engagement metric indicating an extent of engagement of the attendee to the online meeting. Based on the engagement metric indicating that the extent of engagement of the attendee to the online meeting falls below an engagement threshold, a request is provided to disconnect or throttle an audio and/or video stream of the online meeting to and/or from an attendee device associated with the attendee of the online meeting. Efficient meeting management may also be performed by clustering related messages.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventors: Pranavasthitha TANDRA, Hitesh Kumar JHAMB, Vikram GUPTA, Arvind Kumar SINGH, Anubhuti ARUN, Ashutosh TRIPATHI, Kausik GHATAK, Aman RASTOGI
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Publication number: 20240028253Abstract: A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.Type: ApplicationFiled: July 20, 2023Publication date: January 25, 2024Inventors: Avinash Rajagiri, Ching-Huang Lu, Aman Gupta, Shuji Tanaka, Masashi Yoshida, Shinji Sato, Yingda Dong
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Patent number: 11880385Abstract: Updates to projected data subsets may be ordered using conditional operations. When updates to a data set are received, a determination is made according to a schema for a projected subset of the data set as to whether the update is to be propagated to the projected subset of the data set. If the update is to be propagated, a comparison of a version identifier for the update may be made with a version identifier for the subset to determine whether performance of the update is consistent with an ordering of updates performed to the first data set. If the comparison indicates the performance of the update is consistent, then the update may be performed to the projected subset. If not, then the update may not be performed.Type: GrantFiled: September 29, 2020Date of Patent: January 23, 2024Assignee: Amazon Technologies, Inc.Inventors: Sharatkumar Nagesh Kuppahally, Peter Zhivkov, Somasundaram Perianayagam, James Christopher Sorenson, III, Amit Gupta, Shishir Agrawal, Sagar Mundra, Vaibhav Jain, Ajay Kumar, Aman Gupta, Ankur Tyagi
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Publication number: 20240012986Abstract: A computer implemented method includes receiving input from a first collaborator user device to modify a cell in a collaborative spreadsheet being shared with other collaborators and viewable on other collaborator user devices, sending modifications via a real time channel to the other user devices for display of mirror modifications to the cell prior to commitment of the modifications, and providing an identifier of the first collaborative user device for display of a notice that the first user device is associated with the mirror modifications.Type: ApplicationFiled: July 6, 2022Publication date: January 11, 2024Inventors: Meenakshi NAREN, Shashank KAPOOR, Karthik KASOJU, Aman GUPTA, Kshitij Sandeep MINOCHA, Jeet Mukeshkumar PATEL, Sandeep CHOUDRI, Naresh JAIN, Bharath TUMU
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Patent number: 11853569Abstract: Various embodiments set forth techniques for cache warmup. The techniques determining, by a node, identities of one or more target storage blocks of a plurality of storage blocks managed by a storage system, where the node previously cached metadata corresponding to the one or more target storage blocks; receiving the metadata corresponding to the one or more target storage blocks; and storing the metadata corresponding to the one or more target storage blocks in a cache memory of the node.Type: GrantFiled: April 22, 2021Date of Patent: December 26, 2023Assignee: NUTANIX, INC.Inventors: Mohammad Mahmood, Aman Gupta, Gaurav Jain, Anoop Jawahar, Prateek Kajaria
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Patent number: 11832035Abstract: Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.Type: GrantFiled: April 16, 2021Date of Patent: November 28, 2023Assignee: XILINX, INC.Inventors: Aman Gupta, Sagheer Ahmad, Ygal Arbel, Abbas Morshed, Eun Mi Kim
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Publication number: 20230370392Abstract: An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.Type: ApplicationFiled: May 13, 2022Publication date: November 16, 2023Applicant: Xilinx, Inc.Inventors: Krishnan Srinivasan, Sagheer Ahmad, Ygal Arbel, Aman Gupta
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Patent number: 11775417Abstract: A service testing system is disclosed to enable consistent replay of stateful requests on a service whose output depends on the service's execution state prior to the requests. In embodiments, the service implements a compute engine that executes service requests and a storage subsystem that maintains execution states during the execution of stateful requests. When a stateful request is received during testing, the storage subsystem creates an in-memory test copy of the execution state to support execution of the request, and provides the test copy to the compute engine. In embodiments, the storage subsystem will create a separate instance of execution state for each individual test run. The disclosed techniques enable mock execution states to be easily created for testing of stateful requests, in a manner that is transparent to the compute engine and does not impact production execution data maintained by the service.Type: GrantFiled: May 18, 2020Date of Patent: October 3, 2023Assignee: Amazon Technologies, Inc.Inventors: Abhishek Arora, Onkar Walavalkar, Aman Gupta, Xuetao Fan, Kurtis Robert Kuszmaul, Christopher Chandler
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Publication number: 20230308384Abstract: Methods and apparatus relating to transmission on physical channels, such as in networks on chips (NoCs) or between chiplets, are provided. One example apparatus generally includes a higher bandwidth client; a lower bandwidth client; a first destination; a second destination; and multiple physical channels coupled between the higher bandwidth client, the lower bandwidth client, the first destination, and the second destination, wherein the higher bandwidth client is configured to send first traffic, aggregated across the multiple physical channels, to the first destination and wherein the lower bandwidth client is configured to send second traffic, concurrently with sending the first traffic, from the lower bandwidth client, dispersed over two or more of the multiple physical channels, to the second destination.Type: ApplicationFiled: March 25, 2022Publication date: September 28, 2023Inventors: Aman GUPTA, Jaideep DASTIDAR, Jeffrey CUPPETT, Sagheer AHMAD
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Publication number: 20230206010Abstract: Described herein are systems and methods for generating an embedding—a learned representation—for an image. The embedding for the image is derived to capture visual aspects, as well as textual aspects, of the image. An encoder-decoder is trained to generate the visual representation of the image. An optical character recognition (OCR) algorithm is used to identify text/words in the image. From these words, an embedding is derived by performing an average pooling operation on pre-trained embeddings that map to the identified words. Finally, the embedding representing the visual aspects of the image is combined with the embedding representing the textual aspects of the image to generate a final embedding for the image.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Xun Luan, Aman Gupta, Sirjan Kafle, Ananth Sankar, Di Wen, Saurabh Kataria, Ying Xuan, Sakshi Verma, Bharat Kumar Jain, Xue Xia, Bhargavkumar Kanubhai Patel, Vipin Gupta, Nikita Gupta
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Publication number: 20230177146Abstract: Embodiments herein describe offloading encryption activities to a network interface controller/card (NIC) (e.g., a SmartNIC) which frees up server compute resources to focus on executing customer applications. In one embodiment, the smart NIC includes a system on a chip (SoC) implemented on an integrated circuit (IC) that includes an embedded processor. Instead of executing a transport layer security (TLS) stack entirely in the embedded processor, the embodiments herein offload certain TLS tasks to a Public Key Infrastructure (PKI) accelerator such as generating public-private key pairs.Type: ApplicationFiled: December 6, 2021Publication date: June 8, 2023Inventors: Jaideep DASTIDAR, Aman GUPTA, Krishnan SRINIVASAN, Sagheer AHMAD
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Publication number: 20230036531Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.Type: ApplicationFiled: July 29, 2021Publication date: February 2, 2023Applicant: XILINX, INC.Inventors: Krishnan SRINIVASAN, Shishir KUMAR, Sagheer AHMAD, Abbas MORSHED, Aman GUPTA
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Patent number: 11567857Abstract: A service testing system is disclosed to enable consistent replay of stateful requests on a service whose output depends on the service's execution state prior to the requests. In embodiments, the service implements a compute engine that executes service requests and a storage subsystem that maintains execution states during the execution of stateful requests. When a stateful request is received during testing, the storage subsystem creates an in-memory test copy of the execution state to support execution of the request, and provides the test copy to the compute engine. In embodiments, the storage subsystem will create a separate instance of execution state for each individual test run. The disclosed techniques enable mock execution states to be easily created for testing of stateful requests, in a manner that is transparent to the compute engine and does not impact production execution data maintained by the service.Type: GrantFiled: May 18, 2020Date of Patent: January 31, 2023Assignee: Amazon Technologies, Inc.Inventors: Abhishek Arora, Onkar Walavalkar, Aman Gupta, Xuetao Fan, Kurtis Robert Kuszmaul, Christopher Chandler
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Publication number: 20220337923Abstract: Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.Type: ApplicationFiled: April 16, 2021Publication date: October 20, 2022Inventors: Aman GUPTA, Sagheer AHMAD, Ygal ARBEL, Abbas MORSHED, Eun Mi KIM
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Publication number: 20220236872Abstract: Various embodiments set forth techniques for cache warmup. The techniques determining, by a node, identities of one or more target storage blocks of a plurality of storage blocks managed by a storage system, where the node previously cached metadata corresponding to the one or more target storage blocks; receiving the metadata corresponding to the one or more target storage blocks; and storing the metadata corresponding to the one or more target storage blocks in a cache memory of the node.Type: ApplicationFiled: April 22, 2021Publication date: July 28, 2022Inventors: Mohammad MAHMOOD, Aman GUPTA, Gaurav JAIN, Anoop JAWAHAR, Prateek KAJARIA
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Publication number: 20220197855Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Ilya K. Ganusov, Ashish Gupta, Chee Hak Teh, Sean R. Atsatt, Scott Jeremy Weber, Parivallal Kannan, Aman Gupta, Gary Brian Wallichs
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Patent number: 11360880Abstract: A service testing system is disclosed to enable consistent replay of stateful requests on a service whose output depends on the service's execution state prior to the requests. In embodiments, the service implements a compute engine that executes service requests and a storage subsystem that maintains execution states during the execution of stateful requests. When a stateful request is received during testing, the storage subsystem creates an in-memory test copy of the execution state to support execution of the request, and provides the test copy to the compute engine. In embodiments, the storage subsystem will create a separate instance of execution state for each individual test run. The disclosed techniques enable mock execution states to be easily created for testing of stateful requests, in a manner that is transparent to the compute engine and does not impact production execution data maintained by the service.Type: GrantFiled: May 18, 2020Date of Patent: June 14, 2022Assignee: Amazon Technologies, Inc.Inventors: Abhishek Arora, Onkar Walavalkar, Aman Gupta, Xuetao Fan, Kurtis Robert Kuszmaul, Christopher Chandler
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Patent number: 11210206Abstract: A service testing system is disclosed to enable consistent replay of stateful requests on a service whose output depends on the service's execution state prior to the requests. In embodiments, the service implements a compute engine that executes service requests and a storage subsystem that maintains execution states during the execution of stateful requests. When a stateful request is received during testing, the storage subsystem creates an in-memory test copy of the execution state to support execution of the request, and provides the test copy to the compute engine. In embodiments, the storage subsystem will create a separate instance of execution state for each individual test run. The disclosed techniques enable mock execution states to be easily created for testing of stateful requests, in a manner that is transparent to the compute engine and does not impact production execution data maintained by the service.Type: GrantFiled: May 18, 2020Date of Patent: December 28, 2021Assignee: Amazon Technologies, Inc.Inventors: Abhishek Arora, Onkar Walavalkar, Aman Gupta, Xuetao Fan, Kurtis Robert Kuszmaul, Christopher Chandler