Abstract: A method performed by a user equipment (UE) for signaling using satellite access in a 4th generation (4G) or 5th generation (5G) network is provided. The method includes receiving, by the UE, a signal from a first network apparatus associated with a satellite when a feeder link is available between the first network apparatus and the second network apparatus associated with a ground network, storing, by the UE, the signal received from the first network apparatus, and determining, by the UE, a third network apparatus associated with the satellite to transmit a response signaling to a user equipment (UE) upon receiving the signal using the first network apparatus based on an expected location of the UE.

Abstract: Automatic software upgrades for transport layer devices is described. One or more transport layer devices from a device list for upgrading are presented on a user interface (UI). A user, via the UI, selects one or more transport layer devices from a device list for upgrading. Upgrade details for upgrading the one or more transport layer devices selected from the device list for upgrading are received via the UI. Based on the upgrade details, the upgrading of the one or more transport layer devices is initiated. Real-time information returned from the one or more transport layer device during the upgrading of the one or more transport layer devices is presented on the UI. The upgrading of the one or more transport layer devices is validated based on the real-time information.

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Abstract: An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.

Abstract: Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.

Abstract: A gas turbine engine includes a fan section having a plurality of fan blades, the fan section configured to generate an airflow through the gas turbine engine, an airflow passage having a core passage and a bypass passage separate from the core passage, a low-speed shaft coupled to and configured to rotate the plurality of fan blades, and a sensor assembly coupled to the gas turbine engine and configured to detect torsional vibration in the low-speed shaft. The sensor assembly includes a plurality of dynamic pressure sensors in the airflow passage. The plurality of dynamic pressure sensors detect a dynamic pressure of the airflow passage that is indicative of the torsional vibration in the low-speed shaft. A damping system is configured to dampen the torsional vibration in the low-speed shaft based on a correlation of a measured torsional vibration and an experimental torsional vibration.

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

Abstract: Methods for improving operational efficiency include methods for improving inspection efficiency and methods for improving operator efficiency. A method includes determining an inspection efficiency of a plurality of inspectors inspecting devices of a building. A method includes determining an operator efficiency of a plurality of operators in resolving alarms generated by devices in a building. A method includes determining a device inspection score.

Abstract: Methods, systems, and computer-readable media for delivery of log records to stateless clients are disclosed. A record delivery system receives, from a client, a first request to read from a persistent log comprising an ordered sequence of records. The first request is associated with a receiver session. The system sends a first set of records to the client and stores a data structure indicating that the first set of records was sent to the client in the receiver session. The system receives, from the client, a second request to read from the persistent log in the receiver session. Based at least in part on the data structure, the system determines a second set of one or more records in the persistent log. The system sends the second set of records to the client.

Abstract: A method may comprise, for each one of a plurality of destination users, computing a score using a first function based on a probability of a source user performing a source action directed towards the destination user, a second function based on a probability of the destination user performing a destination action in response to the source action, and a third function based on a measure of interaction by the destination user with an online service to result from the destination action being performed by the destination user. The score for inactive users may be boosted using an optimization algorithm with a first constraint comprising a maximum threshold number of the inactive users to display as recommendations to the source user and a second constraint comprising a minimum threshold number of the inactive users for which the source user to perform the source action.

Abstract: Techniques for network-on-chip (NoC) memory addressable encryption and authentication. In an embodiment, NoC circuitry includes NoC routing circuitry, memory circuitry that stores a security parameter, and security circuitry that secures (e.g., encrypts and/or authenticates) a payload based on the security parameter. The security circuitry may secure the payload before the payload is packetized for transmission through the NoC, after the payload is de-packetized for output to an endpoint, or as the payload transits the NoC. The security circuitry may be centralized or distributed amongst access points of the NoC. Distributed security circuitry may exchange a security parameter over a secure link of the NoC circuitry. The security circuitry may include decryption circuitry that decrypts a response from a first endpoint before the response is packetized for transmission through the NoC, after the response is de-packetized for output to a second endpoint, or as the response transits the NoC.

Abstract: In an example embodiment, a deep machine learning model ranks cohorts of users as well as cohorts of products in a single ranking. When utilized to determine which cohort members to display to a user, the system selects one user cohort and one product cohort as the “best” (e.g., the top ranked user cohort and the top ranked product cohort). This ranking may be based on a number of contextual and non-contextual features, including viewer features (characteristics of the user operating the user interface), viewee features (characteristics of or related to the litem that the user is viewing, such as the characteristics of another user whose profile the user is viewing), and viewer-viewee relationship features (indications about how the viewer and viewee are related, such as common schools, locations, places of employment, etc.).

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

Abstract: Embodiments herein describe techniques to extend a network-on-chip (NoC) across multiple IC dice in 3D. An integrated circuit (IC) device includes first and second vertically-stacked IC dice, and an inter-die bus that interfaces between the second die and a NoC packet switch (NPS) of the first die. The inter-die bus may include one or more driver circuits coupled to inter-die links of the inter-die bus. Communications over the inter-die links may be synchronous (e.g., packet-based) or asynchronous with the NPS (e.g., based on a point-to-point protocol, such as an AXI protocol). The inter-die bus may interface with a circuit block of the second IC device via a point-to-point (e.g., AXI) protocol or via a NPS of the second IC die.

Abstract: Embodiments herein describe a memory controller (MC) in a first integrated circuit (IC) that connect to circuitry in the same integrated circuit (e.g., horizontal direction) and to circuitry in a second IC in the vertical direction. That is, the first and second ICs can be stacked on each other where the MC in the first IC provides an interface for both circuitry in the first IC as well as circuitry in the second IC to communicate with a separate memory device. Thus, the MC includes data paths in both the X direction (e.g., within the same IC) and the Y direction (e.g., to an external IC). In this manner, the MC can provide an interface for circuitry in multiple ICs (or dies or chiplets) to the same external memory device.

Abstract: A computer implemented method includes receiving input from a first collaborator user device to modify a cell in a collaborative spreadsheet being shared with other collaborators and viewable on other collaborator user devices, sending modifications via a real time channel to the other user devices for display of mirror modifications to the cell prior to commitment of the modifications, and providing an identifier of the first collaborative user device for display of a notice that the first user device is associated with the mirror modifications.

Abstract: Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.

Abstract: Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.

Abstract: A classifier is trained to classify business supplier relationships using synthetic training data samples. Real training data samples are collected and transformed into sample encodings using an encoder. The real training data samples include feature data associated with health class indicators indicative of relationships between suppliers and service providers. A set of synthetic training data samples is generated from the sample encodings using a generator and discrimination feedback data is generated using a discriminator based on the real training data samples and the synthetic training data samples. The discrimination feedback data is used to train the generator. A classifier model is trained to classify suppliers with health class indicators using the set of synthetic training data samples. The use of the encoder, generator, and discriminator enables the generation of accurate synthetic training data that represents the source distribution of real data which are often partially observed.

Abstract: Methods and apparatus relating to transmission on physical channels, such as in networks on chips (NoCs) or between chiplets, are provided. One example apparatus generally includes a higher bandwidth client; a lower bandwidth client; a first destination; a second destination; and multiple physical channels coupled between the higher bandwidth client, the lower bandwidth client, the first destination, and the second destination, wherein the higher bandwidth client is configured to send first traffic, aggregated across the multiple physical channels, to the first destination and wherein the lower bandwidth client is configured to send second traffic, concurrently with sending the first traffic, from the lower bandwidth client, dispersed over two or more of the multiple physical channels, to the second destination.