Abstract: Methods and computer-storage media are provided for rendering three-dimensional (3D) graphics by tessellating objects using novel structures and algorithms. Rendering utilizing “patches,” configurable functions that include a specified number of control points, allows for computation on a per-patch or per-control-point basis, in addition to traditional per-vertex, per-primitive, and per-pixel methods. This produces a number of advantages over previous tessellation methods, including the reuse of computations across existing vertices and the ability to process at a lower frequency. The operations to compute points are simplified in order to optimize system resources used in the process. Transitions from un-tessellated to tessellated objects are smoother utilizing the present invention, while developers have more flexibility in the level of detail present at different edges of the same patch.

Abstract: Mechanisms for generating an analysis result about a machine are provided. A device generates a first health management (HM) analysis result regarding a machine based on real-time first sensor information received during a first period of time and on a first version HM analytic model. The device provides, to an off-board device, a plurality of sensor information comprising the real-time first sensor information and that is generated during the first period of time. The device receives a second version HM analytic model that is based at least in part on the plurality of sensor information and fault information that identifies actual faults that have occurred on the machine. The device generates a second HM analysis result regarding the machine based on real-time second sensor information received during a second period of time and on the second version HM analytic model.

Abstract: A method for tile-based rendering of content. Content may be rendered in a memory region organized as multiple tiles. In scenarios in which content is generated in layers, for operations that involve compositing image layers, an order in which portions of the image are processed may be selected to reduce the aggregate number of memory accesses times, which in turn may improve the performance of a computer that uses tile-based rendering. An image may be processed such that operations relating to rendering portions of different layers corresponding to the same tile are performed sequentially. Such processing may be used in a computer with a graphics processing unit that supports tile-based rendering, and may be particularly well suited for computers with a slate form factor. An interface to a graphics processing utility within the computer may provide a flag to allow an application to specify whether operations may be reordered.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: Methods, systems, and computer-storage media for target independent rasterization of an image. The target is the memory allocated for a rendered image within a graphics pipeline. Embodiments of the present invention allow the rasterization process's sampling rate to be specified independently from the memory allocated for the rendered image. Embodiments of the present invention also allow the rasterization process to be executed at a rate that does not correspond to the memory allocated for the rendered target.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: Methods and computer-storage media are provided for rendering three-dimensional (3D) graphics by tessellating objects using novel structures and algorithms. Rendering utilizing “patches,” configurable functions that include a specified number of control points, allows for computation on a per-patch or per-control-point basis, in addition to traditional per-vertex, per-primitive, and per-pixel methods. This produces a number of advantages over previous tessellation methods, including the reuse of computations across existing vertices and the ability to process at a lower frequency. The operations to compute points are simplified in order to optimize system resources used in the process. Transitions from un-tessellated to tessellated objects are smoother utilizing the present invention, while developers have more flexibility in the level of detail present at different edges of the same patch.

Abstract: Methods and computer-storage media are provided for rendering three-dimensional (3D) graphics by tessellating objects using novel structures and algorithms. Rendering utilizing “patches,” configurable functions that include a specified number of control points, allows for computation on a per-patch or per-control-point basis, in addition to traditional per-vertex, per-primitive, and per-pixel methods. This produces a number of advantages over previous tessellation methods, including the reuse of computations across existing vertices and the ability to process at a lower frequency. The operations to compute points are simplified in order to optimize system resources used in the process. Transitions from un-tessellated to tessellated objects are smoother utilizing the present invention, while developers have more flexibility in the level of detail present at different edges of the same patch.

Abstract: A system and method for calibrating a set-point for climate control includes a sensor network having a plurality of sensors configured to report a climate condition. A database is configured to receive reports from the sensors and generate one or more profiles reflecting at least one of historic climate control information and occupant preferences. A controller is configured to receive information from the profiles to generate a set-point based upon an optimization program. The optimization program is implemented to balance competing goals to generate the set-point for controlling climate control equipment in accordance with the set-point.

Abstract: A method is provided for developing a product. The method includes obtaining data records from a plurality of stages of development of the product; identifying respective objectives of the plurality of stages and corresponding objective factors of the objectives; and determining common variables associated with the objectives based on the objective factors. The method includes selecting one or more input parameters based on the common variables and one or more output parameters based on the objectives; and updating the data records to generate desired data records indicative characteristics of the one or more input parameters and the one or more output parameters. The method includes generating a computational model indicative of interrelationships between the one or more input parameters and the one or more output parameters based on the data records; and providing a set of constraints to the computational model representative of a design of the product.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: Methods and computer-storage media are provided for rendering three-dimensional (3D) graphics by tessellating objects using novel structures and algorithms. Rendering utilizing “patches,” configurable functions that include a specified number of control points, allows for computation on a per-patch or per-control-point basis, in addition to traditional per-vertex, per-primitive, and per-pixel methods. This produces a number of advantages over previous tessellation methods, including the reuse of computations across existing vertices and the ability to process at a lower frequency. The operations to compute points are simplified in order to optimize system resources used in the process. Transitions from un-tessellated to tessellated objects are smoother utilizing the present invention, while developers have more flexibility in the level of detail present at different edges of the same patch.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: A fluid dispenser includes a container defining a fluid reservoir and having an opening and a dual applicator assembly removably attached to the container. The dual applicator assembly includes a cap adapted to substantially seal the opening. A writing point is disposed in the cap and a stem is coupled to the cap. The stem has first and second ends and includes a channel through the first end. The channel defines a fluid passageway between the writing point and the fluid reservoir. Finally, an applicator is coupled to the second end of the stem.

Abstract: A method is provided for developing a product. The method may include obtaining data records from a plurality of stages of development of the product; identifying respective objectives of the plurality of stages and corresponding objective factors of the objectives; and determining common variables associated with the objectives based on the objective factors. The method may also include selecting one or more input parameters based on the common variables and one or more output parameters based on the objectives; and updating the data records to generate desired data records indicative characteristics of the one or more input parameters and the one or more output parameters. Further, the method may include generating a computational model indicative of interrelationships between the one or more input parameters and the one or more output parameters based on the data records; and providing a set of constraints to the computational model representative of a design of the product.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.