Patents by Inventor Amar Amin

Amar Amin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods for avoiding parasitic capacitance in an integrated circuit package
    Patent number: 8288269
    Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: October 16, 2012
    Assignee: LSI Corporation
    Inventors: Jeffrey Hall, Shawn Nikoukary, Amar Amin, Michael Jenkins
  • Methods for Avoiding Parasitic Capacitance in an Integrated Circuit Package
    Publication number: 20120021599
    Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.
    Type: Application
    Filed: October 4, 2011
    Publication date: January 26, 2012
    Applicant: LSI CORPORATION
    Inventors: Jeffrey Hall, Shawn Nikoukary, Amar Amin, Michael Jenkins
  • Device for avoiding parasitic capacitance in an integrated circuit package
    Patent number: 8049340
    Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: November 1, 2011
    Assignee: LSI Corporation
    Inventors: Jeffrey Hall, Shawn Nikoukary, Amar Amin, Michael Jenkins
  • Wire bond integrated circuit package for high speed I/O
    Patent number: 7804167
    Abstract: An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: September 28, 2010
    Assignee: LSI Logic Corporation
    Inventors: Clifford Fishley, Abiola Awujoola, Leonard Mora, Amar Amin, Maurice Othieno, Chok J. Chia
  • WIRE BOND INTEGRATED CIRCUIT PACKAGE FOR HIGH SPEED I/O
    Publication number: 20080128919
    Abstract: An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 5, 2008
    Inventors: Clifford Fishley, Abiola Awujoola, Leonard Mora, Amar Amin, Maurice Othieno, Chok J. Chia
  • Semiconductor package and method using isolated Vss plane to accommodate high speed circuitry ground isolation
    Publication number: 20070235849
    Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
    Type: Application
    Filed: April 6, 2006
    Publication date: October 11, 2007
    Inventors: Maurice Othieno, Chok Chia, Amar Amin
  • DEVICE FOR AVOIDING PARASITIC CAPACITANCE IN AN INTEGRATED CIRCUIT PACKAGE
    Publication number: 20070222084
    Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.
    Type: Application
    Filed: March 22, 2006
    Publication date: September 27, 2007
    Inventors: Jeffrey Hall, Shawn Nikoukary, Amar Amin, Michael Jenkins