Abstract: The invention provides a method and apparatus for incorporating an appliance into a computer system. One embodiment of the invention has a computer with a first digital wireless transceiver, and an appliance unit with a second digital wireless transceiver for communicatively coupling to the first wireless transceiver. This appliance unit also has (1) an output device, communicatively coupled to the second wireless transceiver, for presenting an output presentation based on signals received from the computer via the wireless transceivers, and (2) an input device, communicatively coupled to the second wireless transceiver, for receiving input signals from a operator of the appliance unit.

Abstract: The invention provides a method and apparatus for incorporating an appliance into a computer system. One embodiment of the invention has a computer with a first digital wireless transceiver, and an appliance unit with a second digital wireless transceiver for communicatively coupling to the first wireless transceiver. This appliance unit also has (1) an output device, communicatively coupled to the second wireless transceiver, for presenting an output presentation based on signals received from the computer via the wireless transceivers, and (2) an input device, communicatively coupled to the second wireless transceiver, for receiving input signals from a operator of the appliance unit.

Abstract: A scheme for sharing a channel during a contention free period of communications between two or more basic service sets (BSSs) including network components in an overlapping region of a wireless computer network. These network components in the overlapping region may be configured to communicate in contention free periods only. Such bandwidth sharing may then include transmitting within each BSS exclusively during an allocated period of time. Each BSS may include one point coordinator network component and all other network components in the BSS then inform the point coordinator of channel conditions including degradation, and the number of packets received from other BSSs.

Abstract: The present invention provides a digital wireless home computer system. One embodiment of the invention includes a computer with a first digital wireless transceiver, and a home input/output node having a second digital wireless transceiver for communicatively coupling to the first wireless transceiver. This node also has (1) an output device, communicatively coupled to the second wireless transceiver, for presenting an output presentation based on signals received from the computer via the wireless transceivers, and (2) an input device, communicatively coupled to the second wireless transceiver, for receiving input signals from a user interfacing with the home input/output node.

Abstract: The invention provides a method and apparatus for incorporating an appliance into a computer system. One embodiment of the invention has a computer with a first digital wireless transceiver, and an appliance unit with a second digital wireless transceiver for communicatively coupling to the first wireless transceiver. This appliance unit also has (1) an output device, communicatively coupled to the second wireless transceiver, for presenting an output presentation based on signals received from the computer via the wireless transceivers, and (2) an input device, communicatively coupled to the second wireless transceiver, for receiving input signals from a operator of the appliance unit.

Abstract: A uniprocessing computer system is provided with an original CPU and an upgrade socket for receiving an additional processor that need not be of a single predetermined type. On system RESET, the original CPU determines if an upgrade processor is resident in the upgrade socket and, if so, what kind of upgrade processor is present. Each upgrade processor is equipped with a programmed data word for identifying the upgrade type and its features. The system includes a mechanism for communicating this upgrade information from the upgrade processor to the original CPU. The processors cooperatively configure the system properly according to the identity and features of the upgrade processor.

Abstract: A cache coherency apparatus for computer systems not having a cache supporting bus is described. The cache coherency apparatus monitors the communication on a bus between a CPU and an external device connected to the bus. The cache coherency apparatus monitors the bus in order to determine when the external device is being programmed by the CPU for a memory modification of a main memory also coupled to the bus. Upon determining that the external device is being programmed for a modification of main memory, the cache coherency apparatus generates cache control signals to a cache memory. Using these cache control signals, the cache coherency apparatus causes the contents of the cache memory to be flushed prior to the memory access performed by the external device. In addition, the cache coherency apparatus generates other cache control signals to disable the locations of main memory being modified from being transferred into the cache memory while the memory access by the external device is taking place.

Abstract: A very large scale integrated (VLSI) chip designed to operate at 3.3 volts is modified to be compatible with prior systems having a 5 volt voltage supply. A central processing unit (CPU) is fabricated at a center position on an integrated circuit chip that has an operating voltage of 3.3 volts. The chip is soldered into a pin grid array (PGA) package and a heat sink is attached on the PGA package above the CPU. A 5 volt-to-3.3 volt voltage regulator having a 5 volt input and a 3.3 volt output is placed at an edge of the PGA package. The 3.3 volt output of the voltage regulator is connected to the 3.3 volt operating voltage input of the chip. The VCC 5 V on board pins are connected to the 5 volt input of the voltage regulator and the 3.3 volt output of the voltage regulator is connected to the VCC pins of the chip. VSS ground on board pins are connected in common to both the ground terminal of the voltage regulator and the VSS pads of the chip.

Abstract: A very large scale integrated (VLSI) chip designed to operate at 3.3 volts is modified to be compatible with prior systems having a 5 volt voltage supply. A central processing unit (CPU) is fabricated at a center position on an integrated circuit chip that has an operating voltage of 3.3 volts. The chip is soldered into a pin grid array (PGA) package and a heat sink is attached on the PGA package above the CPU. A 5 volt- to- 3.3 volt voltage regulator having a 5 volt input and a 3.3 volt output is placed at an edge of the PGA package. The 3.3 volt output of the voltage regulator is connected to the 3.3 volt operating voltage input of the chip. The VCC 5V on board pins are connected to the 5 volt input of the voltage regulator and the 3.3 volt output of the voltage regulator is connected to the VCC pins of the chip.

Abstract: A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

Abstract: Methods and circuitry for sharing a memory space of a microcontroller with a processor. The memory space corresponds to a random access memory accessible by the microcontroller. The memory space includes random access memory on a same substrate as the microcontroller. The processor is located on a different substrate from the microcontroller. The circuitry includes a slave port for communicating data between the processor and the microcontroller. The slave port receives a logical address and a control signal from the processor. The slave port generates an interrupt signal in response to the control signal. An interrupt server generates memory control signals in response to the interrupt signal. A memory controller reads data from and writes data to the slave port and a memory location associated with the logical address in response to the memory control signals.