Abstract: An output buffer includes a first group of stagger FETs coupled in parallel between a power lead and an output signal lead and a second group of stagger FETs coupled in parallel between the output signal lead and a ground lead. Each stagger FET has a gate coupled to a respective base resistor and a respective adjustable resistor. A first group of bypass FETs and a second group of bypass FETs are each coupled across the terminals of a respective adjustable resistor and the gates of the bypass FETs are coupled to either a first process-sensing signal lead or a second process-sensing signal lead.

Abstract: A voltage level translator translates signals between first and second voltage domains. An output buffer for a channel thereof includes a first plurality of PFETs and a first plurality of NFETS that are coupled to provide staggering of the output signal. A supply difference sensing circuit can disable staggering when an input voltage supply is greater than or equal to a VCCI trigger for the output voltage supply.

Abstract: A voltage level translator translates signals between first and second voltage domains. An output buffer for a channel thereof includes a first plurality of PFETs and a first plurality of NFETS that are coupled to provide staggering of the output signal. A supply difference sensing circuit can disable staggering when an input voltage supply is greater than or equal to a VCCI trigger for the output voltage supply.

Abstract: A level shifting circuit for a voltage level translator includes first and second cross-coupled level shifters, each coupled between an output supply voltage and a lower rail and further coupled to receive first and second input control signals and to provide an output control signal. The second cross-coupled level shifter includes a first PMOS transistor coupled in series with a first NMOS transistor and a second PMOS transistor coupled in series with a second NMOS transistor. When an input supply voltage is less than a VCCI trigger associated with the output supply voltage, only the first and second NMOS transistors are coupled to contribute to the output control signal and when the input supply voltage is equal to or greater than the VCCI trigger, only the first and second PMOS transistors are coupled to contribute to the output control signal.

Abstract: A level translator translates signals between first and second voltage domains. An output buffer thereof includes a plurality of PFETs coupled in parallel between a second domain's output supply voltage and an output signal and a plurality of NFETs coupled in parallel between the output signal and the ground rail. Each gate of the plurality of PFETs is coupled to a respective first resistor; the first resistors are coupled in series and receive a first gate control signal. Each gate of the plurality of NFETs is coupled to a respective second resistor; the second resistors are coupled in series and receive a second gate control signal. A first booster NFET is coupled between the output supply voltage and the output signal and a second booster NFET is coupled between the output signal and the ground rail. The booster NFETs receive control signals that operate in the first voltage domain.

Abstract: A level translator translates signals between first and second voltage domains. An output buffer thereof includes a plurality of PFETs coupled in parallel between a second domain's output supply voltage and an output signal and a plurality of NFETs coupled in parallel between the output signal and the ground rail. Each gate of the plurality of PFETs is coupled to a respective first resistor; the first resistors are coupled in series and receive a first gate control signal. Each gate of the plurality of NFETs is coupled to a respective second resistor; the second resistors are coupled in series and receive a second gate control signal. A first booster NFET is coupled between the output supply voltage and the output signal and a second booster NFET is coupled between the output signal and the ground rail. The booster NFETs receive control signals that operate in the first voltage domain.