Patents by Inventor Amar Pal Singh Rana

Amar Pal Singh Rana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9854850
    Abstract: A female crotch enhancing article with cosmetic human female crotch enhancer volume which is positioned within the outer and inner layer of a human female garment's crotch which gives the simulated appearance of exaggerated contours and curves associated with the human female external genitalia without or with the simulated appearance of the exaggerated pudendal cleft associated with the human female external genitalia to provide the human female wearer with subtle understated sexual expression and subtle non-verbal communication.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: January 2, 2018
    Inventors: Amar Pal Singh Rana, Nirmal Singh
  • Patent number: 9044355
    Abstract: An absorbent article to absorb and contain human female bodily excretions from the genitalia for placement in the inner crotch portion of an undergarment of a human female wearer; and with a separate cosmetic human female crotch enhancer element which is positioned on garment faceable side and gives the simulated appearance of exaggerated contours and curves associated with the human female external genitalia with the simulated appearance of exaggerated pudendal cleft associated with the human female external genitalia and without or with the simulated pubic hair to provide the human female wearer with subtle understated sexual expression and subtle non-verbal communication.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: June 2, 2015
    Inventors: Amar Pal Singh Rana, Nirmal Singh
  • Patent number: 7429880
    Abstract: The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipolar action in Strained/Unstrained Silicon-On-Insulator (SOI) circuits, where insulator may be oxide, nitride of Silicon and the like or Sapphire and the like including a method of synthesis.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: September 30, 2008
    Inventors: Amar Pal Singh Rana, Nirmal Singh
  • Patent number: 7360198
    Abstract: The present invention pertains to automated technology dependent transformations for CMOS digital design synthesis resulting in a combination of CMOS interconnected standard-cells from a target CMOS library being mapped and transistor-level representation of the input design specification. The transistor level type and portion to be represented at the transistor level representation is chosen by a user. The transistor sizing and evaluating the combination of said transistor-level representation and standard-cell mapping are performed iteratively to meet delay, size and power constraints for CMOS.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: April 15, 2008
    Inventors: Amar Pal Singh Rana, Nirmal Singh
  • Patent number: 7039882
    Abstract: The present invention pertains to automated technology dependent transformations for Silicon-On-Insulator (SOI) in the digital design synthesis, the transformations include the steps of receiving input design specification in the form of technology independent specification or interconnected library of standard-cells; performing the technology dependent transformations in the digital design synthesis, resulting in interconnected SOI standard-cells from a SOI target library accounting for floating body effects, including floating body effects affecting delays over long periods of simulation time or testing over long times on fabricated SOI library cells, or SOI transistor level representations, transistor sizing and evaluating the standard-cell mapping and transistor-level representation for all or portion of the input design specification iteratively to meet delay and power constraints for SOI.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: May 2, 2006
    Inventors: Amar Pal Singh Rana, Nirmal Singh
  • Publication number: 20040154079
    Abstract: A female crotch enhancing article with or without flaps of the type for placement in the vicinity of a human female's external genitalia; and with separate or integral cosmetic human female crotch enhancer volume which is at least partially or wholly positioned on or within any combination of body facing side, outside and/or within the outer and inner layer of a human female garment's crotch which gives the simulated appearance of exaggerated contours and curves associated with the human female external genitalia without or with the simulated appearance of the exaggerated pudendal cleft associated with the human female external genitalia and/or without or with the simulated pubic hair to provide the human female wearer with subtle understated sexual expression and/or subtle non-verbal communication.
    Type: Application
    Filed: December 30, 2002
    Publication date: August 12, 2004
    Inventors: Amar Pal Singh Rana, Nirmal Singh
  • Publication number: 20040068245
    Abstract: An absorbent article to absorb and/or contain human female bodily excretions from the genitalia for placement in the inner crotch portion of an undergarment or insertable into the interlabial space of a human female wearer; and with separate or integral cosmetic human female crotch enhancer volume which is at least partially or wholly positioned on or within any combination of body facing side, garment facing side and/or absorbent volume of the absorbent article and which gives the simulated appearance of exaggerated contours and curves associated with the human female external genitalia without or with the simulated appearance of exaggerated pudendal cleft associated with the human female external genitalia and/or without or with the simulated pubic hair to provide the human female wearer with subtle understated sexual expression and/or subtle non-verbal communication.
    Type: Application
    Filed: October 4, 2002
    Publication date: April 8, 2004
    Inventors: Amar Pal Singh Rana, Nirmal Singh
  • Publication number: 20030233628
    Abstract: The present invention pertains to automated technology dependent transformations in Silicon-On-Insulator (SOI) during the digital design synthesis, the transformations include the steps of receiving input design specification in the form of technology independent specification and/or interconnected structural blocks, where the structural blocks have been described as a library of standard-cells; performing the technology dependent transformations during the digital design synthesis, resulting in interconnected SOI standard-cells from a SOI target library accounting for floating body effects, including floating body effects affecting delays over long periods of simulation time or testing over long times on fabricated SOI library cells, and/or SOI transistor level representations or a combination thereof, transistor sizing and evaluating the standard-cell mapping and/or transistor-level representation for all or portion of the input design specification iteratively to meet delay and/or power constraints for SOI
    Type: Application
    Filed: June 17, 2002
    Publication date: December 18, 2003
    Inventors: Amar Pal Singh Rana, Nirmal Singh