Abstract: The new architecture disclosed herein exploits advances in system and chip technologies to implement a scalable multi-port open network. Using System-on-a-Chip (SOCs) and/or Multi-Chip-Module (MCM) technology, the architecture is implemented to efficiently handle multi-port switching. The novelty lies in using multi-core computing model in the data, control and management planes of multi-port networking cards implemented as an elemental scalable system (ESS) comprising N number of Elemental Units (EUs). EUs comprise device arrays on an integrated circuit (IC) platform using integrated silicon photonics or discrete electro-optics. TX4M™ system architecture therefore includes multiple EUs, switch fabric, multi-core central processing unit (CPU), multi-port power management module with embedded programmable logic, a back plane interface (BPI) as well as selectable functions for front plane interface (FPI) implemented in FPGAs for integration of front plane interface optics on host or on pluggable modules.

Abstract: A method and apparatus for a voltage reference is provided. The circuit may include one or more of the following features: cascode compensation with load balancing to increase the bandwidth of the amplifier for enhanced power supply rejection ratio; PMOS and NMOS in the input stage to expand common mode, having a high gain over voltage range; current mirror using active resistors; and a start-up circuit. The voltage reference comprises an amplifier having an output, the amplifier comprising a first amplifier stage and a second amplifier stage. The amplifier further includes a power-down circuit coupled to the second amplifier stage to float the amplifier output when a power-down signal is active. The voltage reference includes a source follower, the output of the amplifier coupled to the gate of the source follower, and a bandgap circuit for providing a bandgap voltage.

Abstract: A pseudo-emitter-coupled-logic (PECL) receiver has a wide common-mode range. Two current-mirror CMOS differential amplifiers are used. One amplifier has n-channel differential transistors and a p-channel current mirror, while the second amplifier has p-channel differential transistors and an n-channel current mirror. When the input voltages approach power or ground, one type of differential transistor continues to operate even when the other type shuts off. The outputs of the two amplifiers are connected together and each amplifier receives the same differential input signals. The tail-current transistor is self-biased using the current-mirror's gate-bias. This self biasing of each amplifier eliminates the need for an additional voltage reference and allows each amplifier to adjust its biasing over a wide input-voltage range. Thus the common-mode input range is extended using self biasing and complementary amplifiers.

Abstract: A pseudo-emitter-coupled-logic (PECL) receiver has a wide common-mode range. Two current-mirror CMOS differential amplifiers are used. One amplifier has n-channel differential transistors and a p-channel current mirror, while the second amplifier has p-channel differential transistors and an n-channel current mirror. When the input voltages approach power or ground, one type of differential transistor continues to operate even when the other type shuts off. The outputs of the two amplifiers are connected together and each amplifier receives the same differential input signals. The tail-current transistor is self-biased using the current-mirror's gate-bias. This self biasing of each amplifier eliminates the need for an additional voltage reference and allows each amplifier to adjust its biasing over a wide input-voltage range. Thus the common-mode input range is extended using self biasing and complementary amplifiers.

Abstract: A twisted-pair current driver is implemented in CMOS. EMI from sharp changes in the current driven is reduced by gradually changing the current driven when the inputs change. The current driver is divided into N differential drivers, each driving one-Nth of the total switching current to the twisted pair. Delay lines delay when input changes are sent to each of the four differential drivers, staggering their response. Either binary or multi-level-transition (MLT-3) data can be transmitted. A binary-to-MLT converter uses a dummy flip-flop to match delays and eliminate encoding glitches. Either the binary or the MLT-3 encoded data is coupled to the inputs of the delay lines and the differential drivers. The mid-level for MLT-3 is driven when both the inputs are high, causing the differential drivers to split the current among the two differential outputs to the twisted pair.

Abstract: A differential-output current driver is constructed entirely of CMOS transistors. Pseudo-ECL levels are reached when a standard resistive termination is connected to the outputs. The current driver can also drive a non-standard termination to the PECL levels. The non-standard termination is low power because it does not draw standby current from power to ground. Current from the current sources within the current driver are assigned to either the switching current or the constant current. The constant current is applied directly to the outputs to drive the termination to a bias point. The switching current is applied to a differential pair of transistors which switch the switching current to one or the other of the differential outputs in response to a differential input. The constant current is combined with any switching current output from the differential transistors and applied to the differential outputs to drive the external termination.

Abstract: A current mirror includes a first power supply terminal for receiving a first supply voltage and a second power supply terminal for receiving a second supply voltage. A first mirror transistor has a first current handling terminal, coupled to the first power supply terminals, a second current handling terminal serving as an input terminal for receiving an input current to be mirrored, and a control terminal. A second mirror transistor has a first current handling terminal coupled to the first power supply terminal, a second current handling terminal serving as an output terminal for providing a mirrored output current to a load as a function of the input current to be mirrored, and a control terminal coupled to the control terminal of the first mirror transistor. In a first embodiment, a level shift transistor has a first current handling terminal coupled to the first power supply terminal, a second current handling terminal, and a control terminal coupled to the input terminal.