Patents by Inventor Amaresh Malipatil

Amaresh Malipatil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10948515
    Abstract: A device may include a sensor, a sampling unit, and an interpolator. The sensor may be configured to sense motion and output a sensed signal. The sampling unit may be configured to sample the sensed signal with a sensor clocking signal to generate a plurality of sampled values. The interpolator may be coupled to the sampling unit and may be configured to receive the plurality of sampled values, the sensor clocking signal, and a reference clocking signal external to the device. The interpolator may be configured to interpolate the plurality of sampled values based on the reference clocking signal and further based on the sensor clocking signal to generate a plurality of output values.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: March 16, 2021
    Assignee: InvenSease, Inc.
    Inventors: Sriraman Dakshinamurthy, Michael Perrott, Amaresh Malipatil, William Kerry Keal, Andy F. Milota
  • Publication number: 20180164125
    Abstract: A device may include a sensor, a sampling unit, and an interpolator. The sensor may be configured to sense motion and output a sensed signal. The sampling unit may be configured to sample the sensed signal with a sensor clocking signal to generate a plurality of sampled values. The interpolator may be coupled to the sampling unit and may be configured to receive the plurality of sampled values, the sensor clocking signal, and a reference clocking signal external to the device. The interpolator may be configured to interpolate the plurality of sampled values based on the reference clocking signal and further based on the sensor clocking signal to generate a plurality of output values.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventors: Sriraman Dakshinamurthy, Michael Perrott, Amaresh Malipatil, William Kerry Keal, Andy F. Milota
  • Patent number: 9172526
    Abstract: Described embodiments provide for, in a receiver circuit, an adaptation process that adjusts the IQ-skew automatically to obtain proper eye centering in a data eye, thereby maximizing horizontal margin of the eye. The IQ-skew adaptation algorithm is realized with a ‘biased’ bang-bang phase detector (BBPD) oof a clock and data recovery circuit (CDR) that biases the weights applied to UP and DOWN outputs of the phase detector, rather than treating them equally. By weighting the BBPD UPs and DOWNs differently, the system locks to the left and right inner corners, and thereby is able to locate the center of the inner eye.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: October 27, 2015
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Amaresh Malipatil, Sunil Srinivasa, Vladimir Sindalovsky, Mark Trafford
  • Patent number: 8848769
    Abstract: Embodiments of the present invention allow for adjustment of transmitter amplitude during joint transmitter (TX) and receiver (RX) equalization. During joint TX and RX adaptation, when the receiver requires a gain update, the receiver gain update is masked above or below a preset range. The RX gain update (instruction) is encoded into a transmitter amplitude update (instruction) transferred through back channel communication. The translation of RX gain to TX amplitude update is performed after the RX gain reaches a specified range. Such masking, encoding and translation reserves a certain amount RX gain range to account for RX gain variation due to process, voltage, and temperature (PVT) changes over time, and also to offer better linear equalization in the receiver over a constrained VGA bandwidth.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: September 30, 2014
    Assignee: LSI Corporation
    Inventors: Mohammad Mobin, Vladimir Sindalovsky, Amaresh Malipatil, Thomas F. Gibbons, Jr., Ye Liu, Lane A. Smith
  • Patent number: 8837626
    Abstract: Described embodiments adjust configurable parameters of at least one filter of a communication system. The method includes conditioning, by an analog front end (AFE) of a receiver in the communication system, an input signal applied to the receiver. Sampled values of the conditioned input signal are generated and digitized. An error detection module generates an error signal based on digitized values of the input signal and a target value. A decision feedback equalizer generates an adjustment signal based on the digitized values of the input signal and values of the error signal. A summer subtracts the adjustment signal from the conditioned input signal, generating an adjusted input signal. An adaptation module determines a conditional adaptation signal based on a comparison of sampled values of the adjusted input signal and values of the error signal. The adaptation module adjusts a transfer function of at least one filter based on the conditional adaptation signal.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: September 16, 2014
    Assignee: LSI Corporation
    Inventors: Amaresh Malipatil, Pervez M. Aziz, Mohammad S. Mobin, Ye Liu
  • Patent number: 8731040
    Abstract: Described embodiments provide a method of adjusting configurable parameters of at least one linear equalizer in a communication system. A transmitting device applies an input signal to a receiver. The at least one linear equalizer equalizes the input signal. A sampler generates one or more sampled values of the input signal. A data detector digitizes the sampled values of the input signal. At least one error detection module generates an error signal based on one or more of a plurality of sampled values of the input signal and a target value. An adaptation module determines a gradient signal based on a comparison of one or more of the plurality of sampled values of the input signal and one or more of the plurality of values of the error signal. The adaptation module adjusts a transfer function of the at least one linear equalizer based on the determined gradient signal.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: May 20, 2014
    Assignee: LSI Corporation
    Inventors: Pervez Aziz, Amaresh Malipatil
  • Patent number: 8711906
    Abstract: In described embodiments, a transceiver includes an eye monitor and margin detector having one or more samplers with corresponding logic. One or more programmable provisioning parameters are defined based on a pre-defined minimum target operating margin for acceptable noise and jitter margins. For example, two programmable provisioning parameters, phase and voltage, correspond with thresholds for margin samplers placed within the eye. Initially, the transceiver applies equalization, after which an inner eye of the transceiver, as detected by the eye monitor, is relatively open with some margin for supporting channels. If the receiver margin goes below this target margin, the eye closes, which is registered by the samplers. In the presence of spectrally rich input data, if the receiver margin goes below this target margin, an updated adaptation of equalizer or other circuit parameters might be initiated; else, adaptation is not generally required.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: April 29, 2014
    Assignee: LSI Corporation
    Inventors: Mohammad Mobin, Ye Liu, Amaresh Malipatil
  • Patent number: 8705672
    Abstract: A receiver has an input and a decision feedback equalizer (DFE). The DFE couples to the receiver input and has at least one tap coefficient. An input signal, having a first amplitude level insufficient to cause significant non-linear distortion in the receiver, is applied to the receiver input. After the DFE adapts to the applied input signal having the first amplitude level by adjusting the at least one tap coefficient, the adaptation process is stopped. Then the at least one tap coefficient is scaled by a factor ? and the amplitude of input signal is adjusted to a second amplitude level greater than the first amplitude level by the scale factor ?. Although the second amplitude level might be sufficient to cause significant non-linear distortion in the receiver, the scaled tap coefficient has the correct values for proper DFE operation in the presence of the non-linear distortion.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: April 22, 2014
    Assignee: LSI Corporation
    Inventors: Amaresh Malipatil, Mohammad Mobin, Pervez Aziz, Ye Liu
  • Publication number: 20140098844
    Abstract: Embodiments of the present invention allow for adjustment of transmitter amplitude during joint transmitter (TX) and receiver (RX) equalization. During joint TX and RX adaptation, when the receiver requires a gain update, the receiver gain update is masked above or below a preset range. The RX gain update (instruction) is encoded into a transmitter amplitude update (instruction) transferred through back channel communication. The translation of RX gain to TX amplitude update is performed after the RX gain reaches a specified range. Such masking, encoding and translation reserves a certain amount RX gain range to account for RX gain variation due to process, voltage, and temperature (PVT) changes over time, and also to offer better linear equalization in the receiver over a constrained VGA bandwidth.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: LSI Corporation
    Inventors: Mohammad Mobin, Vladimir Sindalovsky, Amaresh Malipatil, Thomas F. Gibbons, JR., Ye Liu, Lane A. Smith
  • Patent number: 8687682
    Abstract: A communication port and method of adapting a transmit filter in the port to reduce receive errors by a receiver coupled to the transmit filter via a communication channel. The filter has coefficients that are adjusted in response to a first adaptation gain value, decision bits, and receiver error values. During a first time period, the coefficients are adjusted until changes in the coefficients are less than a first threshold amount. Then during a second time period, the coefficients are adjusted using a second adaptation gain value until changes in the coefficients are less than a second threshold amount. The second adaptation gain value is less than the first adaptation gain value and the second threshold amount being less than the first threshold amount. By using two or more adjustment periods with different gain values, the filter is adapted faster than using a single adjustment period with fixed adaptation gain.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: April 1, 2014
    Assignee: LSI Corporation
    Inventors: Mohammad Mobin, Amaresh Malipatil, Adam Healey, Ye Liu
  • Patent number: 8649476
    Abstract: In described embodiments, a transceiver includes a baud-rate clock and data recovery (CDR) module with an eye sampler, and an adaptation module for adaptively setting parameters of various circuit elements, such as timing, equalizer and gain elements. Data sampling clock phase of the CDR module is set for sampling at, for example, near the center of a data eye detected by the eye sampler, and the phase of data error sampling latch(es) is skewed by the CDR module with respect to the phase of the data sampling latch. Since the error signal driving the timing adaptation contains the information of the pulse response that the CDR module encounters, the phase of timing error sampling latch(es) of the CDR module is skewed based on maintaining a relative equivalence of input pulse response residual pre-cursor and residual post-cursor with respect to the timing error sampling clock phase.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: February 11, 2014
    Assignee: LSI Corporation
    Inventors: Amaresh Malipatil, Wingfaat Liu, Ye Liu, Freeman Y. Zhong, Chintan Desai
  • Patent number: 8605847
    Abstract: In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: December 10, 2013
    Assignee: LSI Corporation
    Inventors: Mohammad Mobin, Mark Trafford, Ye Liu, Vladimir Sindalovsky, Amaresh Malipatil
  • Patent number: 8537885
    Abstract: In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained 1T resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with 1T resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: September 17, 2013
    Assignee: LSI Corporation
    Inventors: Pervez Aziz, Hiroshi Kimura, Amaresh Malipatil
  • Publication number: 20130195154
    Abstract: A communication port and method of adapting a transmit filter in the port to reduce receive errors by a receiver coupled to the transmit filter via a communication channel. The filter has coefficients that are adjusted in response to a first adaptation gain value, decision bits, and receiver error values. During a first time period, the coefficients are adjusted until changes in the coefficients are less than a first threshold amount. Then during a second time period, the coefficients are adjusted using a second adaptation gain value until changes in the coefficients are less than a second threshold amount. The second adaptation gain value is less than the first adaptation gain value and the second threshold amount being less than the first threshold amount. By using two or more adjustment periods with different gain values, the filter is adapted faster than using a single adjustment period with fixed adaptation gain.
    Type: Application
    Filed: January 30, 2012
    Publication date: August 1, 2013
    Inventors: Mohammad Mobin, Amaresh Malipatil, Adam Healey, Ye Liu
  • Patent number: 8472513
    Abstract: Disclosed is a method and system that adapts coefficients of taps of a Finite Impulse Response (FIR) filter to increase elimination of Inter-Symbol Interference (ISI) introduced into a digital communications signal due to distortion characteristics caused by a real-world communications channel. In the communications system there is a Finite Impulse Response (FIR) filter. The FIR filter has at least one pre and/or post cursor tap that removes pre and/or post cursor ISI from the signal, respectively. The pre/post cursor taps each have pre/post cursor coefficients, respectively, that adjusts the effect of the pre/post cursor portion of the FIR filter. The FIR filtered signal is transmitted over the channel which distorts the signal due to the changing and/or static distortion characteristics of the channel. The channel distorted signal is received at a receiver that may pass the channel distorted signal through a quantifier/decision system (e.g.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: June 25, 2013
    Assignee: LSI Corporation
    Inventors: Amaresh Malipatil, Lizhi Zhong, Wenyi Jin, Ye Liu
  • Publication number: 20130148712
    Abstract: Described embodiments adjust configurable parameters of at least one filter of a communication system. The method includes conditioning, by an analog front end (AFE) of a receiver in the communication system, an input signal applied to the receiver. Sampled values of the conditioned input signal are generated and digitized. An error detection module generates an error signal based on digitized values of the input signal and a target value. A decision feedback equalizer generates an adjustment signal based on the digitized values of the input signal and values of the error signal. A summer subtracts the adjustment signal from the conditioned input signal, generating an adjusted input signal. An adaptation module determines a conditional adaptation signal based on a comparison of sampled values of the adjusted input signal and values of the error signal. The adaptation module adjusts a transfer function of at least one filter based on the conditional adaptation signal.
    Type: Application
    Filed: December 9, 2011
    Publication date: June 13, 2013
    Inventors: Amaresh Malipatil, Pervez M. Aziz, Mohammad S. Mobin, Ye Liu
  • Publication number: 20130077669
    Abstract: A receiver has an input and a decision feedback equalizer (DFE). The DFE couples to the receiver input and has at least one tap coefficient. An input signal, having a first amplitude level insufficient to cause significant non-linear distortion in the receiver, is applied to the receiver input. After the DFE adapts to the applied input signal having the first amplitude level by adjusting the at least one tap coefficient, the adaptation process is stopped. Then the at least one tap coefficient is scaled by a factor ? and the amplitude of input signal is adjusted to a second amplitude level greater than the first amplitude level by the scale factor ?. Although the second amplitude level might be sufficient to cause significant non-linear distortion in the receiver, the scaled tap coefficient has the correct values for proper DFE operation in the presence of the non-linear distortion.
    Type: Application
    Filed: September 26, 2011
    Publication date: March 28, 2013
    Inventors: Amaresh Malipatil, Mohammad Mobin, Pervez Aziz, Ye Liu
  • Patent number: 8379711
    Abstract: Methods and apparatus are provided for decision-feedback equalization with an oversampled phase detector. A method is provided for detecting data in a receiver employing decision-feedback equalization. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and DFE transition data. One or more coefficients used for the DFE correction for the transition sample signals are adapted using the DFE transition data.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: February 19, 2013
    Assignee: LSI Corporation
    Inventors: Pervez M. Aziz, Adam B. Healey, Amaresh Malipatil, Lizhi Zhong
  • Publication number: 20130039407
    Abstract: In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained IT resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with IT resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.
    Type: Application
    Filed: March 2, 2012
    Publication date: February 14, 2013
    Inventors: Pervez Aziz, Hiroshi Kimura, Amaresh Malipatil
  • Publication number: 20120257652
    Abstract: In described embodiments, a transceiver includes a baud-rate clock and data recovery (CDR) module with an eye sampler, and an adaptation module for adaptively setting parameters of various circuit elements, such as timing, equalizer and gain elements. Data sampling clock phase of the CDR module is set for sampling at, for example, near the center of a data eye detected by the eye sampler, and the phase of data error sampling latch(es) is skewed by the CDR module with respect to the phase of the data sampling latch. Since the error signal driving the timing adaptation contains the information of the pulse response that the CDR module encounters, the phase of timing error sampling latch(es) of the CDR module is skewed based on maintaining a relative equivalence of input pulse response residual pre-cursor and residual post-cursor with respect to the timing error sampling clock phase.
    Type: Application
    Filed: April 7, 2011
    Publication date: October 11, 2012
    Inventors: Amaresh Malipatil, Wingfaat Liu, Ye Liu, Freeman Y. Zhong, Chintan Desai