Abstract: An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.

Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for clock recovery.

Abstract: In order to initialize the phase of the recovered clock signal used in clock-and-data recovery (CDR) circuitry, the normal, on-line CDR processing is disabled. The sum of the absolute values of analog-to-digital converter (ADC) samples are generated for different clock phases over each unit interval (UI) of the analog signal sampled by the ADC for a specified period of time. The phase corresponding to the maximum sum is selected as the initial phase for the recovered clock signal for enabled, on-line CDR processing, which among other things, automatically updates the clock phase to ensure that the ADC samples the analog signal near the center of each UI.

Abstract: An apparatus comprising an equalizer circuit, a converter circuit and an adaptation circuit. The equalizer circuit may be configured to generate an intermediate signal in response to an input signal and a gradient value. The converter circuit may be configured to generate a digital signal comprising a plurality of symbol values, including a main cursor symbol value, in response to the intermediate signal. The adaptation circuit may be configured to generate the gradient value in response to a plurality of the symbol values before the main cursor symbol value, a plurality of symbol values after the main cursor symbol value, and an error value.

Abstract: The present invention includes receiving a signal from an output of a dispersive communication channel established between a transmitter and a receiver, determining normalized Nyquist energy of the signal transmitted along the dispersive communication channel established between the transmitter and the receiver, and generating a mapping table configured to identify peaking value at or above a selected tolerance level at or near the Nyquist frequency for a signal received by the receiver based on the normalized Nyquist energy.

Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for dock recovery.

Abstract: Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.

Abstract: In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.

Abstract: Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.

Abstract: In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.

Abstract: A method for adaptive selection of floating taps in a decision feedback equalizer including the steps of (A) determining values for a predefined metric for tap positions within a range covered by a decision feedback equalizer (DFE) and (B) setting one or more floating taps of the DFE to tap positions based upon the values of the predefined metric.

Abstract: An apparatus generally having a first circuit and a second circuit. The first circuit may be configured to (i) generate an equalizer parameter in response to an input signal, the equalizer parameter causing a cancellation of post-cursor inter-symbol interference from a plurality of symbols in the input signal and (ii) generate an output signal in response to both the input signal and the equalizer parameter. The second circuit may be configured to (i) generate a target parameter signal in response to the input signal, the target parameter signal representing a mean value of a plurality of sample points of the symbols and (ii) generate a control signal in response to the target parameter signal, the control signal causing a reduction of the equalizer parameter, the reduction causing a decrease in the cancellation of the post-cursor inter-symbol interference from the symbols, wherein the apparatus does not cancel pre-cursor inter-symbol interference.

Abstract: An apparatus generally having a first circuit and a second circuit. The first circuit may be configured to (i) generate an equalizer parameter in response to an input signal, the equalizer parameter causing a cancellation of post-cursor inter-symbol interference from a plurality of symbols in the input signal and (ii) generate an output signal in response to both the input signal and the equalizer parameter. The second circuit may be configured to (i) generate a target parameter signal in response to the input signal, the target parameter signal representing a mean value of a plurality of sample points of the symbols and (ii) generate a control signal in response to the target parameter signal, the control signal causing a reduction of the equalizer parameter, the reduction causing a decrease in the cancellation of the post-cursor inter-symbol interference from the symbols, wherein the apparatus does not cancel pre-cursor inter-symbol interference.