Patents by Inventor Amarjeet Kumar
Amarjeet Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20260089903Abstract: In one embodiment, a housing is coupled to a device connector (e.g., an M.2-compatible expansion slot) on a circuit board. The housing may be a conductive material (e.g., metal) and sized to cover a device coupled to the connector such that the device may be substantially encompassed by the housing and the circuit board. The housing may contact, directly or indirectly, the device to provide thermal transfer. In addition, the housing may be connected to ground to provide electromagnetic interference (EMI) shielding of the device.Type: ApplicationFiled: August 19, 2025Publication date: March 26, 2026Applicant: Intel CorporationInventors: Ezekiel Poulose, Avinash Manu Aravindan, Prakash Kurma Raju, Amarjeet Kumar, Tejasweeni D. Lingayat, Prasanna Pichumani, Nehakausar A. Mansuri, Arumanayagam Rajasekar, Bala Subramanya, Jayprakash Thakur
-
Patent number: 12300918Abstract: A connector to connect an electronic module to an edge of a first electronic circuit board is described. The module has a second electronic circuit board. The connector has a top part that houses a first row of I/Os. The top part is to be placed on a surface of the first electronic circuit board. The connector has a bottom part that houses a second row of I/Os. The bottom part is to be placed on an opposite surface of the first electronic circuit board, wherein, the top and bottom parts form inner and outer stand-offs when mater together. The inner stand-off is to reside within a through hole of the first electronic circuit board. The outer stand-off is to reside within free space off the edge of the first electronic circuit board. The second electronic circuit board is to be pressed in between the first row of I/Os and the second row of I/Os when the module is connected to the connector.Type: GrantFiled: September 20, 2021Date of Patent: May 13, 2025Assignee: Intel CorporationInventors: Navneet Kumar Singh, Aiswarya M. Pious, Richard S. Perry, Amarjeet Kumar, Siva Prasad Jangili Ganga, Gaurav Hada, Sushil Padmanabhan, Konika Ganguly
-
Patent number: 12025971Abstract: An apparatus includes a memory interposer including a socket including an inner surface, one or more memories disposed on the inner surface, a bottom surface opposite to the inner surface, and pogo pins disposed on the bottom surface and respectively corresponding to the one or more memories, the pogo pins being configured to connect the one or more memories to a printed circuit board (PCB) including a semiconductor die. The apparatus further includes an intermediate thermal head attached to the memory interposer. The memory interposer is movable with respect to the intermediate thermal head.Type: GrantFiled: February 9, 2022Date of Patent: July 2, 2024Assignee: Intel CorporationInventors: Navneet Singh, Samarth Alva, Amarjeet Kumar, Gaurav Hada
-
Publication number: 20240006873Abstract: Systems, apparatuses and methods may provide for power adapter technology that includes an adapter plug having a housing, a plurality of contacts positioned within the housing, wherein the plurality of contacts includes one or more configuration channel contacts, and a piezoelectric membrane positioned on an external surface of the housing, wherein the piezoelectric membrane is electrically connected to the one or more configuration channel contacts. Additionally, sink device technology may detect a signal from the piezoelectric membrane of the adapter plug via the configuration channel contact(s), wherein the signal indicates user contact with the adapter plug, and disconnect a bulk capacitor from a receptacle adjacent to the adapter plug in response to a disconnect condition associated with the user contact.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Navneet Kumar Singh, Shailendra Singh Chauhan, Aiswarya Pious, Amarjeet Kumar, Samarth Alva
-
Publication number: 20230367027Abstract: A method for estimating noise in particle motion seismic recordings and upgoing (deghosted) and downgoing components of ecorded wavefields includes inputting pressure related and particle motion related seismic signals. A sparsity promoting transformation is applied to the input seismic signals. A matrix à and column vector {tilde over (b)} are constructed according to the expression: A ~ = ( I I 0 I - I ? ? I ) x ~ = ( d u n ) b ~ = ( A - 1 ? p A - 1 ? z ) , wherein d represents a down-going seismic wavefield, u represents an up-going seismic wavefield, n represents the noise and ? represents a user-chosen scalar to adjust emphasis of the noise.Type: ApplicationFiled: July 10, 2023Publication date: November 16, 2023Inventors: Gary Hampson, Amarjeet Kumar, Tom Rayment
-
Publication number: 20230299516Abstract: A back-to-back ultra-slim module (USM) includes an inline USM (USMi) connector and a top mount USM (USMt) connector. The back-to-back USM assembly can be made as a double-sided module to allow a stacked module configuration to save system area. The stacked module has a USMi module inline with the system board on one side of the system board, and a USMt module vertically offset from the other side of the system board. The stacked module can have a thermal layer between the USMi module and the USMt module.Type: ApplicationFiled: May 25, 2023Publication date: September 21, 2023Applicant: Intel CorporationInventors: Amarjeet KUMAR, Navneet Kumar SINGH, I, Samarth ALVA, Richard S. PERRY, Christopher WEST
-
Publication number: 20230251629Abstract: An apparatus includes a memory interposer including a socket including an inner surface, one or more memories disposed on the inner surface, a bottom surface opposite to the inner surface, and pogo pins disposed on the bottom surface and respectively corresponding to the one or more memories, the pogo pins being configured to connect the one or more memories to a printed circuit board (PCB) including a semiconductor die. The apparatus further includes an intermediate thermal head attached to the memory interposer. The memory interposer is movable with respect to the intermediate thermal head.Type: ApplicationFiled: February 9, 2022Publication date: August 10, 2023Inventors: Navneet SINGH, Samarth ALVA, Amarjeet KUMAR, Gaurav HADA
-
Publication number: 20230198568Abstract: Embodiments of the present disclosure are directed to antenna switching systems. For example, some embodiments may include a switching system to allow a computing system to switch between an internal antenna and an external antenna. Other embodiments may be described and claimed.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Inventors: Maruti Tamrakar, Jayprakash Thakur, Sagar Gupta, Rajasekar Arumanayagam, Amarjeet Kumar
-
Publication number: 20220077609Abstract: A connector to connect an electronic module to an edge of a first electronic circuit board is described. The module has a second electronic circuit board. The connector has a top part that houses a first row of I/Os. The top part is to be placed on a surface of the first electronic circuit board. The connector has a bottom part that houses a second row of I/Os. The bottom part is to be placed on an opposite surface of the first electronic circuit board, wherein, the top and bottom parts form inner and outer stand-offs when mater together. The inner stand-off is to reside within a through hole of the first electronic circuit board. The outer stand-off is to reside within free space off the edge of the first electronic circuit board. The second electronic circuit board is to be pressed in between the first row of I/Os and the second row of I/Os when the module is connected to the connector.Type: ApplicationFiled: September 20, 2021Publication date: March 10, 2022Inventors: Navneet Kumar SINGH, Aiswarya M. PIOUS, Richard S. PERRY, Amarjeet KUMAR, Siva Prasad JANGILI GANGA, Gaurav HADA, Sushil PADMANABHAN, Konika GANGULY
-
Patent number: 11221426Abstract: A method for deblending seismic signals includes entering as input to a computer recorded signals comprising seismic energy from a plurality of actuations of one or more seismic energy sources. A model of deblended seismic data and a blending matrix are initialized. A blending matrix inversion is performed using the initialized model. The inversion includes using a scaled objective function. The inversion is constrained by a thresholding operator. The thresholding operator is arranged to recover coefficients of the model of the deblended seismic data that are substantially nonzero, against a Gaussian white noise background. The thresholded model is projected into data space. Performing the blending matrix inversion is repeated if a data residual exceeds a selected threshold and the inversion is terminated if the data residual is below the selected threshold. At least one of storing and displaying an output of the blending matrix inversion is performed when the blending matrix inversion is terminated.Type: GrantFiled: November 25, 2019Date of Patent: January 11, 2022Assignee: DownUnder GeoSolutions Pty Ltd.Inventors: Amarjeet Kumar, Gary Hampson, Troy A. Thompson
-
Publication number: 20200096661Abstract: A method for deblending seismic signals includes entering as input to a computer recorded signals comprising seismic energy from a plurality of actuations of one or more seismic energy sources. A model of deblended seismic data and a blending matrix are initialized. A blending matrix inversion is performed using the initialized model. The inversion includes using a scaled objective function. The inversion is constrained by a thresholding operator. The thresholding operator is arranged to recover coefficients of the model of the deblended seismic data that are substantially nonzero, against a Gaussian white noise background. The thresholded model is projected into data space. Performing the blending matrix inversion is repeated if a data residual exceeds a selected threshold and the inversion is terminated if the data residual is below the selected threshold. At least one of storing and displaying an output of the blending matrix inversion is performed when the blending matrix inversion is terminated.Type: ApplicationFiled: November 25, 2019Publication date: March 26, 2020Inventors: Amarjeet Kumar, Gary Hampson, Troy A. Thompson
-
Publication number: 20190235116Abstract: A method for attenuating multiple reflections from marine seismic signals includes estimating a multichannel prediction filter by minimizing energy between detected seismic signals and seismic signals representing water layer multiple reflections in combination with forcing a sparsity constraint on the estimated multichannel filter. Near offset seismic signals not present in the detected seismic signals are reconstructed by convolving the detected seismic signals with an inverse of the multichannel prediction filter. The multichannel prediction filter is convolved with the reconstructed near offset seismic signals to obtain a final multiple reflection model. The final multiple reflection model is subtracted from the detected seismic signals to obtain multiple reflection attenuated seismic signals.Type: ApplicationFiled: April 12, 2019Publication date: August 1, 2019Inventors: Amarjeet Kumar, Gary A. Hampson, Troy Thompson