Patents by Inventor Amarjit Singh Bhandal

Amarjit Singh Bhandal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100232480
    Abstract: A semiconductor device is described. The device comprises a transmitter associated with a die; a package adapted to be coupled to the transmitter and operative for receiving a data signal from the transmitter, wherein the package comprises at least one package trace having at least one segment, and the segment is capacitive and is positioned a quarter wavelength away from the die; a channel adapted to be coupled to the package and operative for receiving the data signal from the package; and a receiver coupled to the channel and operative for receiving the data signal from the channel.
    Type: Application
    Filed: November 26, 2009
    Publication date: September 16, 2010
    Inventors: Amarjit Singh Bhandal, Brian Young
  • Patent number: 7039795
    Abstract: A method for processing data using a multiplexing architecture includes performing a selected one of a plurality of first multiplexer operations on the data and then a selected one of a plurality of second multiplexer operations. The first multiplexer operations include a pass operation and a plurality of bit rearrangement operations. The second multiplexer operations include a pass operation and a plurality of bit duplication operations which duplicates a selected bit or bits to a corresponding block of contiguous bits in the output. A result is then generated that reflects the outputs produced by first and second multiplexers respectively.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: May 2, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Keith Balmer, Karl M. Guttag, Amarjit Singh Bhandal
  • Patent number: 6711602
    Abstract: An embodiment of the invention includes a pair of parallel 16×16 multipliers each with two 32-bit inputs and one 32-bit output. There are options to allow input halfword and byte selection for four independent 8×8 or two independent 16×16 multiplications, real and imaginary parts of comple×multiplication, pairs of partial sums for 32×32 multiplication, and partial sums for 16×32 multiplication. There are options to allow internal hardwired routing of each multiplier unit results to achieve partial-sum shifting as required to support above options. There is a redundant digit arithmetic adder before final outputs to support additions for partial sum accumulation, complex multiplication vector accumulation and general accumulation for FIRs/IIRs—giving MAC unit functionality. There are options controlled using bit fields in a control register passed to the multiplier unit as an operand.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: March 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Amarjit Singh Bhandal, Keith Balmer, David Hoyle, Karl M. Guttag, Zahid Hussain
  • Publication number: 20030233529
    Abstract: A method for processing data using a multiplexing architecture is provided that includes performing a selected one of a plurality of first multiplexer operations on the data such that a first output is produced. The method also includes performing a selected one of a plurality of second multiplexer operations on the first output such that a second output is produced. A result is then generated that reflects the first and second outputs produced by first and second multiplexers respectively.
    Type: Application
    Filed: June 14, 2002
    Publication date: December 18, 2003
    Applicant: Texas Instruments Incorporated
    Inventors: Keith Balmer, Karl M. Guttag, Amarjit Singh Bhandal