Patents by Inventor Amarnath Shanmugam

Amarnath Shanmugam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus for improving read stability
    Patent number: 9922702
    Abstract: Described is an apparatus which comprises: a pass-gate; a sleep transistor configured as a diode-connected device controllable by the pass-gate; and a word-line driver coupled to the sleep transistor and the pass-gate.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Amarnath Shanmugam, Anik Basu, Steve P. Ferrera, Srinivas Rajamani, Feroze A. Merchant
  • Integrated circuit memory with word line driving helper circuits
    Patent number: 8014226
    Abstract: An integrated circuit memory 2 incorporates a first array of bit cells 4 and a second array of bit cells 6 with word line driver circuitry 8 disposed therebetween. Word line helper circuitry 18, 20 is disposed at the opposite edges of the array 4, 6 to the word line driver circuitry 8. The helper circuitry is responsive to the word line signal on a word line 12 being driven towards an asserted value to switch on and further drive the word line signal towards the asserted value. The helper circuitry is switched off by a global reset signal, which may be a self-timed global reset signal.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: September 6, 2011
    Assignee: ARM Limited
    Inventors: Gus Yeung, Amarnath Shanmugam, Yew Keong Chong, Jacek Wiatrowski
  • Integrated circuit memory with word line driving helper circuits
    Publication number: 20110149674
    Abstract: An integrated circuit memory 2 incorporates a first array of bit cells 4 and a second array of bit cells 6 with word line driver circuitry 8 disposed therebetween. Word line helper circuitry 18, 20 is disposed at the opposite edges of the array 4, 6 to the word line driver circuitry 8. The helper circuitry is responsive to the word line signal on a word line 12 being driven towards an asserted value to switch on and further drive the word line signal towards the asserted value. The helper circuitry is switched off by a global reset signal, which may be a self-timed global reset signal.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Inventors: Gus Yeung, Amarnath Shanmugam, Yew Keong Chong, Jacek Wiatrowski