Patents by Inventor Amarnath Thulabanthula

Amarnath Thulabanthula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230394213
    Abstract: A method, system, and computer program product for parallel regression to bypass regression process interruption are provided. The method identifies an RTL design. The RTL design is converted into a control data flow graph having a plurality of nodes and a plurality of arcs. A mapping table is generated with a machine learning database from a set of test cases based on the control data flow graph. The method selectively calls one or more test cases of the set of test cases to merge a branch to a main repository to bypass a portion of a regression process.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 7, 2023
    Inventors: Kousik Dan, Sandeep Korrapati, Joji P George, Amarnath Thulabanthula, Nitish Jindal, Madhuri Soma
  • Patent number: 11790143
    Abstract: A method, system, and computer program product for parallel regression to bypass regression process interruption are provided. The method identifies an RTL design. The RTL design is converted into a control data flow graph having a plurality of nodes and a plurality of arcs. A mapping table is generated with a machine learning database from a set of test cases based on the control data flow graph. The method selectively calls one or more test cases of the set of test cases to merge a branch to a main repository to bypass a portion of a regression process.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: October 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Kousik Dan, Sandeep Korrapati, Joji P George, Amarnath Thulabanthula, Nitish Jindal, Madhuri Soma
  • Publication number: 20220398368
    Abstract: A method, system, and computer program product for parallel regression to bypass regression process interruption are provided. The method identifies an RTL design. The RTL design is converted into a control data flow graph having a plurality of nodes and a plurality of arcs. A mapping table is generated with a machine learning database from a set of test cases based on the control data flow graph. The method selectively calls one or more test cases of the set of test cases to merge a branch to a main repository to bypass a portion of a regression process.
    Type: Application
    Filed: June 15, 2021
    Publication date: December 15, 2022
    Inventors: Kousik Dan, Sandeep Korrapati, Joji P. George, Amarnath Thulabanthula, Nitish Jindal, Madhuri Soma
  • Patent number: 10902169
    Abstract: A method, system, and computer program product are described for use with graph-based verification of a circuit design. The method comprises performing, using a graph referencing the circuit design, a predefined set of one or more test sequences. The method further comprises determining that a first coverage point of the graph is not fully hit by the predefined set, and back-traversing the graph from a second coverage point of the graph that is partially hit or fully hit by the predefined set. The method further comprises generating, based on back-traversing the graph, a prospective test sequence to fully hit the first coverage point.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Joji P. George, Kousik Dan, Nitish Jindal, Sandeep Korrapati, Amarnath Thulabanthula