Abstract: In some aspects, the present disclosure provides a method for power management. The method includes receiving, by a power management unit (PMU), signaling indicative of a first plurality of latency durations from a first plurality of clients, each of the first plurality of latency durations corresponding to one of the first plurality of clients, wherein each of the first plurality of clients is configured to utilize a first shared resource for communication of data. In certain aspects, the method also includes selecting, by the PMU, a first latency duration from the first plurality of latency durations based on a determination that the first latency duration is the shortest latency duration of the first plurality of latency durations, and transitioning, by the PMU, the first shared resource from an active state to the first idle state.

Abstract: In some aspects, the present disclosure provides a method for power management. The method includes receiving, by a power management unit (PMU), signaling indicative of a first plurality of latency durations from a first plurality of clients, each of the first plurality of latency durations corresponding to one of the first plurality of clients, wherein each of the first plurality of clients is configured to utilize a first shared resource for communication of data. In certain aspects, the method also includes selecting, by the PMU, a first latency duration from the first plurality of latency durations based on a determination that the first latency duration is the shortest latency duration of the first plurality of latency durations, and transitioning, by the PMU, the first shared resource from an active state to the first idle state.

Abstract: The proposed technique provides simultaneous read and writes from a display controller using low-cost SDRAMs. This is achieved, in one example embodiment, by receiving a sequence of video frames at a first variable frame rate. A first video frame is then written in a first single-ported memory. The first video frame is then read from the first single-ported memory upon completing the writing of the first video frame in the first single-ported memory. The reading of the first video frame is then repeated from the first single-ported memory to maintain a second frame rate. The second frame rate is higher than the first variable frame rate. A second video frame is then written in a second single-ported memory upon completing the writing of the first video frame in the first single-ported memory such that the writing of the first video frame and the second video frame is at the first variable frame rate.

Abstract: The proposed technique provides simultaneous read and writes from a display controller using low-cost SDRAMs. This is achieved, in one example embodiment, by receiving a sequence of video frames at a first variable frame rate. A first video frame is then written in a first single-ported memory. The first video frame is then read from the first single-ported memory upon completing the writing of the first video frame in the first single-ported memory. The reading of the first video frame is then repeated from the first single-ported memory to maintain a second frame rate. The second frame rate is higher than the first variable frame rate. A second video frame is then written in a second single-ported memory upon completing the writing of the first video frame in the first single-ported memory such that the writing of the first video frame and the second video frame is at the first variable frame rate.