Abstract: A by-pass circuit includes a first power MOS with an intrinsic diode, a first conduction terminal coupled to a cathode, a second conduction terminal coupled to an anode, and a control terminal. A tank capacitor is coupled to the anode. A second MOS has a first and second conduction terminals, a control terminal, and a turn-on threshold smaller than that of the intrinsic diode, the first conduction terminal thereof coupled to the cathode and the control terminal coupled to the anode, so the first MOS turns on when the array of cells are sub-illuminated. An oscillator and charge pump are supplied through the second conduction terminal of the second MOS to charge the tank capacitor. A control circuit is coupled to the control terminal of the first power MOS to switch it based upon a voltage of the tank capacitor and sign of the voltage between the cathode and anode.

Abstract: A device for calculating the quotient q and remainder r of the division (y·k1+x)/k2, wherein k1 and k2 are integers and constant, and wherein x and y are integers. The device comprises a first digital circuit for receiving as input values of y and identifying corresponding values of the quotient qy and the remainder ry of the function y·k1/k2, a second digital circuit for calculating the remainder r of the division, by a) calculating a combined value (x+ry) of the remainder ry and the value of x, b) verifying if the combined value (x+ry) is less than k2, c) correcting the combined value (x+ry) if the verification indicates that the combined value (x+ry) is not less than k2, and d) assigning the corrected combined value (x+ry) to the remainder r, a third digital circuit for calculating the quotient q of the division, by a) correcting the quotient qy if the verification (2206) indicates that the combined value (x+ry) is not less than k2, and b) assigning the corrected quotient qy to the quotient q.

Abstract: A device for calculating the quotient q and remainder r of the division (y·k1+x)/k2, wherein k1 and k2 are integers and constant, and wherein x and y are integers. The device comprises a first digital circuit for receiving as input values of y and identifying corresponding values of the quotient qy and the remainder ry of the function y·k1/k2, a second digital circuit for calculating the remainder r of the division, by a) calculating a combined value (x+ry) of the remainder ry and the value of x, b) verifying if the combined value (x+ry) is less than k2, c) correcting the combined value (x+ry) if the verification indicates that the combined value (x+ry) is not less than k2, and d) assigning the corrected combined value (x+ry) to the remainder r, a third digital circuit for calculating the quotient q of the division, by a) correcting the quotient qy if the verification (2206) indicates that the combined value (x+ry) is not less than k2, and b) assigning the corrected quotient qy to the quotient q.

Abstract: A by-pass circuit includes a first power MOS with an intrinsic diode, a first conduction terminal coupled to a cathode, a second conduction terminal coupled to an anode, and a control terminal. A tank capacitor is coupled to the anode. A second MOS has a first and second conduction terminals, a control terminal, and a turn-on threshold smaller than that of the intrinsic diode, the first conduction terminal thereof coupled to the cathode and the control terminal coupled to the anode, so the first MOS turns on when the array of cells are sub-illuminated. An oscillator and charge pump are supplied through the second conduction terminal of the second MOS to charge the tank capacitor. A control circuit is coupled to the control terminal of the first power MOS to switch it based upon a voltage of the tank capacitor and sign of the voltage between the cathode and anode.

Abstract: Management of Test Access Port functions of a plurality of components arranged on a single chip by selectively driving the TAP function of each of the components with respective clocks, whilst the further signals for driving the TAP function are used in a shared mode among the various components. Preferably, associated with the aforesaid clocks is a pull-down function for selectively blanking the respective clocks in conditions of non-use. In a preferred way, the aforesaid dedicated clocks are generated on board the chip.

Abstract: Management of Test Access Port functions of a plurality of components arranged on a single chip by selectively driving the TAP function of each of the components with respective clocks, whilst the further signals for driving the TAP function are used in a shared mode among the various components. Preferably, associated with the aforesaid clocks is a pull-down function for selectively blanking the respective clocks in conditions of non-use. In a preferred way, the aforesaid dedicated clocks are generated on board the chip.