Patents by Inventor Ameen D. Akel
Ameen D. Akel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240411466Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.Type: ApplicationFiled: August 19, 2024Publication date: December 12, 2024Inventors: Yang Lu, Sujeet Ayyapureddi, Edmund J. Gieske, Cagdas Dirik, Ameen D. Akel, Elliott C. Cooper-Balis, Amitava Majumdar, Robert M. Walker, Danilo Caraccio
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Publication number: 20240404581Abstract: Methods, systems, and devices for interface techniques for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute memory access circuitry among multiple semiconductor dies of a stack. A first die of the system may include logic circuitry operable to configure a set of multiple first interface blocks of the first die. Each first interface block may include circuitry operable to communicate with one or more second interface blocks of one or more second dies of the system to access a respective set of one or more memory arrays of the one or more second dies. In some examples, the system may include a respective controller for each first interface block to support access operations via the first interface block. The system may also include non-volatile storage, one or more sensors, or a combination thereof to support various operations of the system.Type: ApplicationFiled: May 17, 2024Publication date: December 5, 2024Inventors: Ameen D. Akel, Brent Keeth, James Brian Johnson, Chun-Yi Liu, Shivasankar Gunasekaran, Paul A. Laberge, Gregory A. King, Sai Krishna Mylavarapu, Su Wei Lim, Nathan A. Eckel, Lance P. Johnson, Nathan D. Henningson
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Publication number: 20240396573Abstract: Methods, systems, and devices for associative computing for error correction are described. A device may receive first data representative of a first codeword of a size for error correction. The device may identify a set of content-addressable memory cells that stores data representative of a set of codewords each of which is the size of the first codeword. The device may identify second data representative of the first codeword in the set of content-addressable memory cells. Based on identifying the second data, the device may transmit an indication of a valid codeword that is mapped to the second data.Type: ApplicationFiled: May 30, 2024Publication date: November 28, 2024Inventors: Ameen D. Akel, Helena Caminal, Sean S. Eilert
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Publication number: 20240370208Abstract: A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.Type: ApplicationFiled: July 19, 2024Publication date: November 7, 2024Inventors: Kenneth Marion Curewitz, Shivam Swami, Samuel E. Bradshaw, Justin M. Eno, Ameen D. Akel, Sean Stephen Eilert
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Patent number: 12136448Abstract: Methods, systems, and devices for memory accessing with auto-precharge are described. For example, a memory system may be configured to support an activate with auto-precharge command, which may be associated with a memory device opening a page of memory cells, latching respective logic states stored by the memory cells at a row buffer, writing logic states back to the page of memory cells, and maintaining the latched logic states at the row buffer (e.g., while maintaining power to latches of the row buffer, after closing the page of memory cells, while the page of memory cells is closed).Type: GrantFiled: June 22, 2022Date of Patent: November 5, 2024Assignee: Micron Technology, Inc.Inventors: Shivam Swami, Sean S. Eilert, Ameen D. Akel
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Publication number: 20240345957Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.Type: ApplicationFiled: June 21, 2024Publication date: October 17, 2024Inventors: Kenneth Marion Curewitz, Ameen D. Akel, Samuel E. Bradshaw, Sean Stephen Eilert, Dmitri Yudanov
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Publication number: 20240338149Abstract: Methods, systems, and devices for schedule memory are described. Specifically, techniques are described for a memory interface between a host system and memory (e.g., a tightly coupled memory). For example, a memory interface block (MIB) between the host system and the memory system may schedule access operations performed by the memory system, schedule and perform error control operations, schedule and perform media management operations, as well as schedule and perform other operations. The use of such a MIB may enable the improvement of the memory system by reducing latency and increasing efficiency of memory accesses, while reducing impacts on the architecture and design of the host system.Type: ApplicationFiled: March 15, 2024Publication date: October 10, 2024Inventors: Chun-Yi Liu, Ameen D. Akel, Lance P. Johnson
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Patent number: 12105589Abstract: Methods, systems, and devices for parity-based error management are described. A processing system that performs a computational operation on a set of operands may perform a computational operation, (e.g., the same computational operation) on parity bits for the operands. The processing system may then use the parity bits that result from the computational operation on the parity bits to detect, and discretionarily correct, one or more errors in the output that results from the computational operation on the operands.Type: GrantFiled: February 23, 2022Date of Patent: October 1, 2024Assignee: Micron Technology, Inc.Inventors: Ameen D. Akel, Helena Caminal, Sean S. Eilert
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Patent number: 12086078Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.Type: GrantFiled: August 15, 2022Date of Patent: September 10, 2024Assignee: Micron Technology, Inc.Inventors: Samuel E. Bradshaw, Shivam Swami, Sean Stephen Eilert, Justin M. Eno, Ameen D. Akel
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Patent number: 12073110Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.Type: GrantFiled: September 12, 2022Date of Patent: August 27, 2024Assignee: Micron Technology, Inc.Inventors: Justin Eno, Sean S. Eilert, Ameen D. Akel, Kenneth M. Curewitz
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Publication number: 20240281167Abstract: Methods, systems, and devices for in-memory associative processing for vectors are described. A device may perform a computational operation on a first set of contiguous bits of a first vector and a first set of contiguous bits of a second vector. The first sets of contiguous bits may be stored in a first plane of a memory die and the computational operation may be based on a truth table for the computational operation. The device may perform a second computational operation on a second set of contiguous bits of the first vector and a second set of contiguous bits of the second vector. The second sets of contiguous bits may be stored in a second plane of the memory die and the computational operation based on the truth table for the computational operation.Type: ApplicationFiled: April 29, 2024Publication date: August 22, 2024Inventors: Sean S. Eilert, Ameen D. Akel, Justin Eno, Brian Hirano
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Patent number: 12067270Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.Type: GrantFiled: September 16, 2022Date of Patent: August 20, 2024Assignee: Micron Technology, Inc.Inventors: Yang Lu, Sujeet Ayyapureddi, Edmund J. Gieske, Cagdas Dirik, Ameen D. Akel, Elliott C. Cooper-Balis, Amitava Majumdar, Robert M. Walker, Danilo Caraccio
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Publication number: 20240273349Abstract: Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.Type: ApplicationFiled: April 22, 2024Publication date: August 15, 2024Inventors: Dmitri Yudanov, Sean S. Eilert, Hernan A. Castro, Ameen D. Akel
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Publication number: 20240248852Abstract: Systems, methods and apparatuses of distributed computing based on memory as a service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.Type: ApplicationFiled: April 1, 2024Publication date: July 25, 2024Inventors: Ameen D. Akel, Samuel E. Bradshaw, Kenneth Marion Curewitz, Sean Stephen Eilert, Dmitri Yudanov
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Patent number: 12045503Abstract: A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.Type: GrantFiled: October 29, 2021Date of Patent: July 23, 2024Assignee: Micron Technology, Inc.Inventors: Kenneth Marion Curewitz, Shivam Swami, Samuel E. Bradshaw, Justin M. Eno, Ameen D. Akel, Sean S. Eilert
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Publication number: 20240237363Abstract: Methods, systems, and devices for modular die configurations for multi-channel memory are described. A semiconductor component (e.g., a semiconductor wafer) may be configured with multiple rows and multiple columns of memory arrays, and associated channels. A row of memory arrays may be associated with a contact region extending along the row direction. The semiconductor component may also include control regions extending along the column direction between at least some of the columns of memory arrays. Each control region may include control circuitry for operating memory arrays on one or both sides of the control region. The channels and memory arrays of the semiconductor wafer may be grouped into one or more independently-operable memory dies, with each memory die having at least a portion of a control region and at least a portion of a contact region for operating the memory arrays of the memory die.Type: ApplicationFiled: December 29, 2023Publication date: July 11, 2024Inventors: James Brian Johnson, Brent Keeth, Ameen D. Akel, Kunal R. Parekh, Amy Rae Griffin, Eiichi Nakano
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Publication number: 20240233870Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.Type: ApplicationFiled: October 25, 2022Publication date: July 11, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: Justin Eno, Sean S. Eilert, Ameen D. Akel, Kenneth M. Curewitz
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Publication number: 20240233869Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.Type: ApplicationFiled: October 25, 2022Publication date: July 11, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: Justin Eno, Sean S. Eilert, Ameen D. Akel, Kenneth M. Curewitz
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Publication number: 20240232601Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (SNN), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.Type: ApplicationFiled: February 20, 2024Publication date: July 11, 2024Inventors: Dmitri Yudanov, Sean S. Eilert, Hernan A. Castro, Ameen D. Akel
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Patent number: 12019549Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.Type: GrantFiled: January 12, 2022Date of Patent: June 25, 2024Assignee: Micron Technology, Inc.Inventors: Kenneth Marion Curewitz, Ameen D. Akel, Samuel E. Bradshaw, Sean Stephen Eilert, Dmitri Yudanov