Abstract: A method and apparatus for decoding an input MPEG video stream are provided that includes a core processor with a very long instruction word (VLIW) processor and a co-processor that includes a variable length decoder (VLD) for decoding the MPEG video stream. The input MPEG video stream is organized into macroblocks, wherein each macroblock includes a header for a macroblock that is not decoded, and encoded data for a macroblock whose header is previously decoded by VLD. Thereafter, VLD decodes the encoded video data of a first macroblock whose header has been decoded, and decodes the header of a second (current) macroblock. VLIW then performs motion compensation on a current macroblock based upon reference data of a previously decoded macroblock. VLIW also adds a fake slice start code and fake macroblock data at the end of each picture into the input MPEG video data stream; and utilizes the fake slice start code and fake macroblock data to skip to a next slice.

Abstract: In methods and systems consistent with the present invention, the process of inverse quantization is performed by determining class number and quantization number for each block of received quantized DCT coefficients, determining a first shift value based on the class number and quantization number and a second shift value based on the class number and a combination type, and shifting the entire block of DCT coefficients based on the first and second shift values. Alternatively, the inverse quantization may be combined with inverse weighting step by pre-shifting a set of weighting tables, one for each area number combination. A pre-shifted weighting matrix is then selected based on the second shift value and multiplied by the shifted matrix of DCT coefficients. In another embodiment, a pre-shifted weighting table is selected based on the class number and combination type and then multiplied by the shifted matrix of DCT coefficients.

Abstract: A method and apparatus for decoding an input MPEG video stream are provided that includes a core processor with a very large instruction word (VLIW) processor and a co-processor that includes a variable length decoder (VLD) for decoding the MPEG video stream. The input MPEG video stream is organized into macroblocks, wherein each macroblock includes a header for a macroblock that is not decoded, and encoded data for a macroblock whose header is previously decoded by VLD. Thereafter, VLD decodes the encoded video data of a first macroblock whose header has been decoded, and decodes the header of a second (current) macroblock. VLIW then performs motion compensation on a current macroblock based upon reference data of a previously decoded macroblock. VLIW also adds a fake slice start code and fake macroblock data at the end of each picture into the input MPEG video data stream; and utilizes the fake slice start code and fake macroblock data to skip to a next picture.

Abstract: A multiple symbol length lookup table is described. The multiple symbol length lookup table includes a plurality of lookup entries and a plurality of lookup results, each lookup entry having a corresponding lookup result. Each lookup entry comprises a particular sequence of input data bits. The input data bits are encoded with a variable length coding. Moreover, the input data bits form one or more consecutive variable length symbols. Each lookup result comprises a total length of the consecutive variable length symbols in the input data bits. In an embodiment, the multiple symbol length lookup table is generated by using a single symbol length lookup table. In practice, the input data bits are submitted to the multiple symbol length lookup table as a lookup entry. In response, the multiple symbol length lookup table returns a lookup result that is the total length or number of bits in the input data bits that a variable length decoder can decode.

Abstract: A method and system for decoding and reconstructing an incoming MPEG video data stream for producing decoded MPEG video data is provided. The method and system utilizes a first memory storage device with at least two memory buffers associated with a co-processor, and a second memory device with a plurality of memory buffers associated with a core-processor. Also provided is a first data transfer unit coupled to the first memory storage device and the second memory device. The first data transfer unit in response to a first signal from the core processor selects one of the first memory storage device buffer (B0) as a source and a buffer in the second memory storage device as a destination buffer (MB_B0′). The data transfer unit is adapted to read content from B0 and write the content of B0 to MB_B0′.

Abstract: A multiple symbol length lookup table is described. The multiple symbol length lookup table includes a plurality of lookup entries and a plurality of lookup results, each lookup entry having a corresponding lookup result. Each lookup entry comprises a particular sequence of input data bits. The input data bits are encoded with a variable length coding. Moreover, the input data bits form one or more consecutive variable length symbols. Each lookup result comprises a total length of the consecutive variable length symbols in the input data bits. In an embodiment, the multiple symbol length lookup table is generated by using a single symbol length lookup table. In practice, the input data bits are submitted to the multiple symbol length lookup table as a lookup entry. In response, the multiple symbol length lookup table returns a lookup result that is the total length or number of bits in the input data bits that a variable length decoder can decode.

Abstract: A system and method for performing a coefficient reconstruction in a decoder. The method comprises receiving a transmitted coefficient of a first block. The method also comprises retrieving a former reconstructed value. Additionally, the method comprises executing a first arithmetic operation to generate a reconstructed value of the transmitted coefficient. The first arithmetic operation is performed using the transmitted coefficient and the former reconstructed value. Finally, the method comprises replacing the former reconstructed value with the new reconstructed value.

Abstract: In methods and systems consistent with the present invention, the process of inverse quantization is performed by determining class number and quantization number for each block of received quantized DCT coefficients, determining a first shift value based on the class number and quantization number and a second shift value based on the class number and a combination type, and shifting the entire block of DCT coefficients based on the first and second shift values. Alternatively, the inverse quantization may be combined with inverse weighting step by pre-shifting a set of weighting tables, one for each area number combination. A pre-shifted weighting matrix is then selected based on the second shift value and multiplied by the shifted matrix of DCT coefficients. In another embodiment, a pre-shifted weighting table is selected based on the class number and combination type and then multiplied by the shifted matrix of DCT coefficients.

Abstract: A variable length code decoder includes modified VLC decode tables as compared to table b.14 and b.15 of Annex B of the ISO/IEC 31818-2 standard, and improved program code for inverse quantising block DCT coefficients. The modified VLC decoding tables include level values corresponding to VLC coded words that have been pre-multiplied by the value 2, or by 2 then plus 1. As a result, the modified tables of the present invention reduces the computational complexity of the inverse quantization calculation of the method of the present invention as compared to the algorithm provided in ISO/IEC 31818-2, section 7. Advantageously, the bandwidth requirement of the inverse quantiser processor is reduced as compared to the bandwidth requirement of an inverse processor executing the inverse quantization calculation as defined in the Standard. Conveniently, lower cost, and more widely available processors may be used in the decoder of the present invention.