Patents by Inventor Amey Anand ZARE

Amey Anand ZARE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10176085
    Abstract: A method and system is provided for automated generation of the functional test cases for testing a software system. In an embodiment, the invention provides an expressive decision table (EDT), a requirement specification notation designed to reduce translation efforts. It implements a novel scalable row-guided random algorithm with fuzzing (RGRaF) (pronounced R-graph) to generate test cases. The invention also implements two new coverage criteria targeted at requirements and requirement interactions. The invention also provides fuzzing at time boundaries to achieve scalability. According to an embodiment, the invention also provides the feature of generating error in case the generated functional test case corresponds to system property violation of the software system. According to another embodiment, the system can also reject the functional test case if there is an improbable condition of the software system.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: January 8, 2019
    Assignee: Tata Consultancy Services Limited
    Inventors: Amey Anand Zare, Venkatesh R, Ulka Aniruddha Shrotri, Supriya Agrawal
  • Publication number: 20160378646
    Abstract: A method and system is provided for automated generation of the functional test cases for testing a software system. In an embodiment, the invention provides an expressive decision table (EDT), a requirement specification notation designed to reduce translation efforts, it implements a novel scalable row-guided random algorithm with fuzzing (RGRaF) (pronounced R-graph) to generate test cases. The invention also implements two new coverage criteria targeted at requirements and requirement interactions. The invention also provides fuzzing at time boundaries to achieve scalability. According to an embodiment, the invention also provides the feature of generating error in case the generated functional test case corresponds to system property violation of the software system. According to another embodiment, the system can also reject the functional test case if there is an improbable condition of the software system.
    Type: Application
    Filed: June 22, 2016
    Publication date: December 29, 2016
    Applicant: Tata Consultancy Services Limited
    Inventors: Amey Anand ZARE, Venkatesh R., Ulka Aniruddha Shrotri, Supriya Agrawal
  • Patent number: 9141511
    Abstract: Disclosed are a method and a system for facilitating verification of program code implementing Sleep Wakeup protocol for a microcontroller. An input handling module is configured to receive metadata from user required for verification of the program code. Identification module is configured to identify abstract syntax tree (AST) nodes corresponding to each program point in the program code. A computation module is configured to compute an actual interrupt protection status (IPS), task lock status (TLS), path entities and shared variables for each program point in the program code. A path analysis module is configured to determine transition paths between program points specified in the metadata, and are computed in terms of the path entities. Also, review information is computed for each of the path entities comprised in the transition paths. Further, a report generation module is configured to generate a report comprising the review information facilitating the user to verify the program code.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: September 22, 2015
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Tukaram B. Muske, Advaita Datar, Amey Anand Zare
  • Publication number: 20150052504
    Abstract: Disclosed are a method and a system for facilitating verification of program code implementing Sleep Wakeup protocol for a microcontroller. An input handling module is configured to receive metadata from user required for verification of the program code. Identification module is configured to identify abstract syntax tree (AST) nodes corresponding to each program point in the program code. A computation module is configured to compute an actual interrupt protection status (IPS), task lock status (TLS), path entities and shared variables for each program point in the program code. A path analysis module is configured to determine transition paths between program points specified in the metadata, and are computed in terms of the path entities. Also, review information is computed for each of the path entities comprised in the transition paths. Further, a report generation module is configured to generate a report comprising the review information facilitating the user to verify the program code.
    Type: Application
    Filed: July 21, 2014
    Publication date: February 19, 2015
    Inventors: Tukaram B. MUSKE, Advaita DATAR, Amey Anand ZARE