Patents by Inventor Ami Dabush

Ami Dabush has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for gating a clock signal
    Patent number: 8384437
    Abstract: A semiconductor device comprising clock gating logic. The clock gating logic comprises clock freezing logic arranged to receive a selected clock signal and an enable signal. The clock freezing logic is further arranged to output a gated clock signal substantially corresponding to the selected clock signal when the enable signal comprises an inactive state, and to freeze the output gated clock signal when the enable signal comprises an active state. The clock gating logic further comprises polarity comparison logic arranged to compare polarities of an input clock signal and the gated clock signal and selector logic arranged to select from the input clock signal and an inverted input clock signal, based on a result of a comparison of the polarities of the input clock signal and the gated clock signal and to provide the selected clock signal to the clock freezing logic.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: February 26, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sergey Sofer, Ami Dabush, Michael Priel
  • METHOD AND APPARATUS FOR GATING A CLOCK SIGNAL
    Publication number: 20110156752
    Abstract: A semiconductor device comprising clock gating logic. The clock gating logic comprises clock freezing logic arranged to receive a selected clock signal and an enable signal. The clock freezing logic is further arranged to output a gated clock signal substantially corresponding to the selected clock signal when the enable signal comprises an inactive state, and to freeze the output gated clock signal when the enable signal comprises an active state. The clock gating logic further comprises polarity comparison logic arranged to compare polarities of an input clock signal and the gated clock signal and selector logic arranged to select from the input clock signal and an inverted input clock signal, based on a result of a comparison of the polarities of the input clock signal and the gated clock signal and to provide the selected clock signal to the clock freezing logic.
    Type: Application
    Filed: September 15, 2008
    Publication date: June 30, 2011
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Sergey Sofer, Ami Dabush, Michael Priel