Patents by Inventor Ami Sato

Ami Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260150347
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer over the semiconductor layer, and a conductive layer over the first insulating layer. The semiconductor layer includes a first region, a pair of second regions, a pair of third regions, and a pair of fourth regions. The second regions sandwich the first region, the third regions sandwich the first region and the second regions, and the fourth regions sandwich the first region, the second regions, and the third regions. The first region includes a region overlapping with the first insulating layer and the conductive layer, the second regions and the third regions each include a region overlapping with the first insulating layer and not overlapping with the conductive layer, and the fourth regions overlap with neither the first insulating layer nor the conductive layer.
    Type: Application
    Filed: January 22, 2026
    Publication date: May 28, 2026
    Inventors: Naoto GOTO, Naoki IKEZAWA, Masataka NAKADA, Ami SATO, Chieko MISAWA
  • Patent number: 12568654
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer over the semiconductor layer, and a conductive layer over the first insulating layer. The semiconductor layer includes a first region, a pair of second regions, a pair of third regions, and a pair of fourth regions. The second regions sandwich the first region, the third regions sandwich the first region and the second regions, and the fourth regions sandwich the first region, the second regions, and the third regions. The first region includes a region overlapping with the first insulating layer and the conductive layer, the second regions and the third regions each include a region overlapping with the first insulating layer and not overlapping with the conductive layer, and the fourth regions overlap with neither the first insulating layer nor the conductive layer.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 3, 2026
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoto Goto, Naoki Ikezawa, Masataka Nakada, Ami Sato, Chieko Misawa
  • Publication number: 20250359155
    Abstract: A semiconductor device that occupies a small area is provided. The semiconductor device includes a first conductive layer, a second conductive layer over the first conductive layer, a first insulating layer over the second conductive layer, a semiconductor layer and a third conductive layer over the first insulating layer, a second insulating layer over the semiconductor layer and the third conductive layer, and a fourth conductive layer over the second insulating layer; at least part of the second conductive layer is in contact with a top surface of the first conductive layer; the semiconductor layer is in contact with the top surface of the first conductive layer, a side surface of the second conductive layer, the third conductive layer, and a side surface of the first insulating layer; and the fourth conductive layer overlaps with the semiconductor layer with the second insulating layer therebetween.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 20, 2025
    Inventors: Masami JINTYOU, Takahiro IGUCHI, Chieko MISAWA, Ami SATO, Junichi KOEZUKA
  • Publication number: 20250234652
    Abstract: A semiconductor device having a high degree of integration is provided. A first and second transistors which are electrically connected to each other and a first insulating layer are included. The first transistor includes a first semiconductor layer, a second insulating layer, and a first to third conductive layers. The second transistor includes a second semiconductor layer, a third insulating layer, and a fourth to sixth conductive layers. The first insulating layer is positioned over the first conductive layer and includes an opening reaching the first conductive layer. The second conductive layer is positioned over the first insulating layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, an inner wall of the opening, and the second conductive layer. The third conductive layer is positioned over the second insulating layer to overlap with the inner wall of the opening. The third insulating layer is positioned over the fourth conductive layer.
    Type: Application
    Filed: April 10, 2023
    Publication date: July 17, 2025
    Inventors: Yasuharu HOSAKA, Takahiro IGUCHI, Chieko MISAWA, Ami SATO, Masayoshi DOBASHI, Masami JINTYOU
  • Publication number: 20250221037
    Abstract: A semiconductor device (10) having a high degree of integration is provided. A first and a second transistors which are electrically connected to each other and a first insulating layer (110) are included. The first transistor (M2) includes a first semiconductor layer (108), a second insulating layer (106), and a first to a third conductive layers. The second transistor (M1) includes a second semiconductor layer (109), a third insulating layer (106), and a fourth to a sixth conductive layers. The first insulating layer is positioned over the first conductive layer (112a) and includes an opening reaching the first conductive layer. The second conductive layer (112b) is positioned over the first insulating layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, an inner wall of the opening, and the second conductive layer. The third conductive layer (104) is positioned over the second insulating layer to overlap with the inner wall of the opening.
    Type: Application
    Filed: April 3, 2023
    Publication date: July 3, 2025
    Inventors: Yasuharu HOSAKA, Takahiro IGUCHI, Chieko MISAWA, Ami SATO, Masayoshi DOBASHI, Masami JINTYOU
  • Publication number: 20250169180
    Abstract: A semiconductor device having a high degree of integration is provided. The semiconductor device includes a first and a second transistor, and an insulating layer. The first transistor includes a source electrode, a drain electrode over the insulating layer over the source electrode, a first semiconductor layer in contact with a top surface of the source electrode, an inner wall of an opening provided in the insulating layer, and a top surface of the drain electrode, a first gate insulating layer in contact with a top surface and a side surface of the first semiconductor layer, and a first gate electrode over the first gate insulating layer that includes a region overlapping with the inner wall of the opening.
    Type: Application
    Filed: March 6, 2023
    Publication date: May 22, 2025
    Inventors: Yasuharu HOSAKA, Masami JINTYOU, Takahiro IGUCHI, Chieko MISAWA, Ami SATO, Masayoshi DOBASHI
  • Patent number: 11940703
    Abstract: A liquid crystal display device with a high aperture ratio is provided. The display device includes a transistor, a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer, a pixel electrode, a common electrode, and a liquid crystal layer in a pixel. The first insulating layer is positioned over a channel formation region of the transistor. The first conductive layer is positioned over the first insulating layer. The second insulating layer is positioned over the transistor, the first insulating layer, and the first conductive layer. The pixel electrode is positioned over the second insulating layer, the third insulating layer is positioned over the pixel electrode, the common electrode is positioned over the third insulating layer, and the liquid crystal layer is positioned over the common electrode. The common electrode includes a region overlapping with the first conductive layer with the pixel electrode positioned therebetween.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kouhei Toyotaka, Kazunori Watanabe, Susumu Kawashima, Kei Takahashi, Koji Kusunoki, Masataka Nakada, Ami Sato
  • Publication number: 20230350256
    Abstract: A liquid crystal display device with a high aperture ratio is provided. The display device includes a transistor, a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer, a pixel electrode, a common electrode, and a liquid crystal layer in a pixel. The first insulating layer is positioned over a channel formation region of the transistor. The first conductive layer is positioned over the first insulating layer. The second insulating layer is positioned over the transistor, the first insulating layer, and the first conductive layer. The pixel electrode is positioned over the second insulating layer, the third insulating layer is positioned over the pixel electrode, the common electrode is positioned over the third insulating layer, and the liquid crystal layer is positioned over the common electrode. The common electrode includes a region overlapping with the first conductive layer with the pixel electrode positioned therebetween.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 2, 2023
    Inventors: Kouhei TOYOTAKA, Kazunori WATANABE, Susumu KAWASHIMA, Kei TAKAHASHI, Koji KUSUNOKI, Masataka NAKADA, Ami SATO
  • Publication number: 20230320135
    Abstract: Provided is a semiconductor device having a high degree of integration, which includes first and second transistors and a first insulating layer. The first transistor includes a first semiconductor layer, a second insulating layer, and first to third conductive layers. The second transistor includes a second semiconductor layer, a third insulating layer, and fourth to sixth conductive layers. The first insulating layer includes a region in contact with the first semiconductor layer and the first conductive layer and includes an opening reaching the first conductive layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, an inner wall of the opening, and the second conductive layer. The second conductive layer is positioned over the first insulating layer. The third conductive layer is positioned over the first semiconductor layer and includes a region overlapping with the inner wall of the opening with the second insulating layer positioned therebetween.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 5, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuharu HOSAKA, Masami JINTYOU, Takahiro IGUCHI, Chieko MISAMA, Ami SATO, Masayoshi DOBASHI
  • Patent number: 11733574
    Abstract: A liquid crystal display device with a high aperture ratio is provided. The display device includes a transistor, a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer, a pixel electrode, a common electrode, and a liquid crystal layer in a pixel. The first insulating layer is positioned over a channel formation region of the transistor. The first conductive layer is positioned over the first insulating layer. The second insulating layer is positioned over the transistor, the first insulating layer, and the first conductive layer. The pixel electrode is positioned over the second insulating layer, the third insulating layer is positioned over the pixel electrode, the common electrode is positioned over the third insulating layer, and the liquid crystal layer is positioned over the common electrode. The common electrode includes a region overlapping with the first conductive layer with the pixel electrode positioned therebetween.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: August 22, 2023
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kouhei Toyotaka, Kazunori Watanabe, Susumu Kawashima, Kei Takahashi, Koji Kusunoki, Masataka Nakada, Ami Sato
  • Publication number: 20220320340
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer over the semiconductor layer, and a conductive layer over the first insulating layer. The semiconductor layer includes a first region, a pair of second regions, a pair of third regions, and a pair of fourth regions. The second regions sandwich the first region, the third regions sandwich the first region and the second regions, and the fourth regions sandwich the first region, the second regions, and the third regions. The first region includes a region overlapping with the first insulating layer and the conductive layer, the second regions and the third regions each include a region overlapping with the first insulating layer and not overlapping with the conductive layer, and the fourth regions overlap with neither the first insulating layer nor the conductive layer.
    Type: Application
    Filed: July 27, 2020
    Publication date: October 6, 2022
    Inventors: Naoto GOTO, Naoki IKEZAWA, Masataka NAKADA, Ami SATO, Chieko MISAWA
  • Publication number: 20210096409
    Abstract: A liquid crystal display device with a high aperture ratio is provided. The display device includes a transistor, a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer, a pixel electrode, a common electrode, and a liquid crystal layer in a pixel. The first insulating layer is positioned over a channel formation region of the transistor. The first conductive layer is positioned over the first insulating layer. The second insulating layer is positioned over the transistor, the first insulating layer, and the first conductive layer. The pixel electrode is positioned over the second insulating layer, the third insulating layer is positioned over the pixel electrode, the common electrode is positioned over the third insulating layer, and the liquid crystal layer is positioned over the common electrode. The common electrode includes a region overlapping with the first conductive layer with the pixel electrode positioned therebetween.
    Type: Application
    Filed: December 25, 2018
    Publication date: April 1, 2021
    Inventors: Kouhei TOYOTAKA, Kazunori WATANABE, Susumu KAWASHIMA, Kei TAKAHASHI, Koji KUSUNOKI, Masataka NAKADA, Ami SATO
  • Patent number: 10217776
    Abstract: A semiconductor device including a capacitor having an increased charge capacity without decreasing an aperture ratio is provided. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, and a pixel electrode electrically connected to the transistor. In the capacitor, a conductive film formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the pixel electrode serves as the other electrode, and a nitride insulating film and a second oxide insulating film which are provided between the light-transmitting semiconductor film and the pixel electrode serve as the a dielectric film.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 26, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Katayama, Ami Sato, Yukinori Shima
  • Publication number: 20170018578
    Abstract: A semiconductor device including a capacitor having an increased charge capacity without decreasing an aperture ratio is provided. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, and a pixel electrode electrically connected to the transistor. In the capacitor, a conductive film formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the pixel electrode serves as the other electrode, and a nitride insulating film and a second oxide insulating film which are provided between the light-transmitting semiconductor film and the pixel electrode serve as the a dielectric film.
    Type: Application
    Filed: September 30, 2016
    Publication date: January 19, 2017
    Inventors: Shunpei YAMAZAKI, Masahiro KATAYAMA, Ami SATO, Yukinori SHIMA
  • Patent number: 9478535
    Abstract: A semiconductor device including a capacitor having an increased charge capacity without decreasing an aperture ratio is provided. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, and a pixel electrode electrically connected to the transistor. In the capacitor, a conductive film formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the pixel electrode serves as the other electrode, and a nitride insulating film and a second oxide insulating film which are provided between the light-transmitting semiconductor film and the pixel electrode serve as the a dielectric film.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: October 25, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Katayama, Ami Sato, Yukinori Shima
  • Publication number: 20140061654
    Abstract: A semiconductor device including a capacitor having an increased charge capacity without decreasing an aperture ratio is provided. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, and a pixel electrode electrically connected to the transistor. In the capacitor, a conductive film formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the pixel electrode serves as the other electrode, and a nitride insulating film and a second oxide insulating film which are provided between the light-transmitting semiconductor film and the pixel electrode serve as the a dielectric film.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 6, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Katayama, Ami Sato, Yukinori Shima