Abstract: The presently disclosed subject matter includes a computerized method and computerized system, which enables to detect usage of a screen reader, by modifying screen reader functionality of elements in a webpage.

Abstract: The presently disclosed subject matter includes a computerized method and computerized system, which enables to detect usage of a screen reader, by modifying screen reader functionality of elements in a webpage.

Abstract: A programmable digital signal processor usable in a variety of configurations and controlled by stored coefficients and control words which are addressable to be provided to a plurality of processing sections as often as once per clock cycle. The processor arrangement is suitable for use as a decoder of multiple analog component (MAC) television signals.

Abstract: A multiplierless digital FIR filter comprising a plurality of serially cascaded stages providing a non-linear series of two to the Nth power coefficient values, and in which quantization error is reduced by scaling the coefficient values to minimize root mean square error. Each stage includes a basic unit and an incremental unit, the basic unit providing two shift operations and including a delay element and an adder. To achieve a particular quantization error, one or more incremental units are connected in series with the basic unit in each stage, each such incremental unit providing a single shift operation and including a delay element and an adder. The number of incremental units in each stage and the number of cascaded stages can be selected to achieve a filter having desired performance characteristics and which can be realized on a VLSI chip.

Abstract: An architecture for a very large scale integrated (VLSI) implementation of a finite imprise response (FIR) digital filter having no multipliers and a coefficient space limited to powers of two. The filter structure includes a data bus, a coefficient bus and a sum-in bus to each coefficient tap. Each tap has a coefficient and control word register which is loaded during an initialization phase of the filter. Multiplication is provided by a shifter which provides the correct power of two weighting of an input data sample. The weighted data sample at each tap is added to the output of the previous tap. This architecture results in a regular, modular structure which can be cascaded and which is programmable for various data word lengths and coefficient spaces.

Abstract: A color television receiver, having a tuner and associated demodulation circuits for both a main picture signal and a picture-in-picture (PIP) signal, uses a single memory for synchronization and for storing a single subsampled field of the PIP signal. Appropriate circuitry is included to selectively adjust the output of the memory to prevent the possible disorder of lines of the resultant PIP signal on display.