Abstract: In an embodiment, a method performed by one or more computing devices comprises storing, for one or more marketplace associated applications, interaction information that identifies, for each particular application of said one or more marketplace associated applications, a list of devices that interacted with an instance of the particular application; receiving, from a requesting device, a request for a list of offer eligible applications; determining, based on said interaction information, a set of applications associated with the requesting device; based on said determination of the set of applications associated with the requesting device, sending a list of one or more selected eligible applications to the requesting device.

Abstract: In an embodiment, a method performed by one or more computing devices comprises storing, for one or more marketplace associated applications, interaction information that identifies, for each particular application of said one or more marketplace associated applications, a list of devices that interacted with an instance of the particular application; receiving, from a requesting device, a request for a list of offer eligible applications; determining, based on said interaction information, a set of applications associated with the requesting device; based on said determination of the set of applications associated with the requesting device, sending a list of one or more selected eligible applications to the requesting device.

Abstract: In an embodiment, a method performed by one or more computing devices comprises storing, for one or more marketplace associated applications, interaction information that identifies, for each particular application of said one or more marketplace associated applications, a list of devices that interacted with an instance of the particular application; receiving, from a requesting device, a request for a list of offer eligible applications; determining, based on said interaction information, a set of applications associated with the requesting device; based on said determination of the set of applications associated with the requesting device, sending a list of one or more selected eligible applications to the requesting device.

Abstract: Disclosed are embodiments of methods and circuits to generate spread spectrum clocks.

Abstract: A fast lock scheme for phase locked loops and delay locked loops, where apparatus, systems, and methods include a startup circuit that is enabled at the beginning of a startup mode and is disabled upon a phase transition detection in the reference and feedback signals to the phase locked loop or delay locked loop. Further apparatus, systems, and methods enable a first charge pump when a phase transition is detected, and enable a second charge pump when the phase difference between the reference and feedback signals fall within a predetermined range.

Abstract: Disclosed are embodiments of methods and circuits to generate spread spectrum clocks.

Abstract: A fast lock scheme for phase locked loops and delay locked loops, where an embodiment comprises a startup circuit that is enabled at the beginning of a startup mode and is disabled upon a phase transition detection in the reference and feedback signals to the phase locked loop or delay locked loop. Further embodiments enable a first charge pump when a phase transition is detected, and enable a second charge pump when the phase difference between the reference and feedback signals fall within a predetermined range. Other embodiments are described and claimed.

Abstract: Embodiments of the invention relate to a memory control hub (MCH) clock master of an MCH. Typically, in a computer system, a processor is coupled to the MCH by a front-side bus (FSB). Further, an input/output control hub (ICH) is typically coupled to the MCH by a back-side bus or Hub Link. In one embodiment, a host phase locked loop (HPLL) of the MCH clock master receives an FSB clock signal transmitted on the FSB and generates a local synchronous clock signal based upon the FSB clock signal. A delayed lock loop (DLL) of the MCH clock master also receives the FSB clock signal and generates a system clock signal. Particularly, the DLL synchronizes the system clock signal to the local synchronous clock and drives the system clock signal to many different devices on the board.

Abstract: Embodiments of the invention relate to a memory control hub (MCH) clock master of an MCH. Typically, in a computer system, a processor is coupled to the MCH by a front-side bus (FSB). Further, an input/output control hub (ICH) is typically coupled to the MCH by a back-side bus or Hub Link. In one embodiment, a host phase locked loop (HPLL) of the MCH clock master receives an FSB clock signal transmitted on the FSB and generates a local synchronous clock signal based upon the FSB clock signal. A delayed lock loop (DLL) of the MCH clock master also receives the FSB clock signal and generates a system clock signal. Particularly, the DLL synchronizes the system clock signal to the local synchronous clock and drives the system clock signal to many different devices on the board.

Abstract: An address transition detection interface is disclosed for a sensing circuit that determines a state of a memory cell having n possible states, where n is greater than 2, and wherein no decoding logic is required to translate outputs of comparators into binary bits. In the case where n is 4, the sensing circuit includes a first reference corresponding to a first threshold voltage level and a first comparator coupled to the memory cell and to the first reference. The first comparator compares a threshold voltage level of the memory cell to the first reference and provides a first result of the comparison as output. The sensing circuit further includes a second reference corresponding to a second threshold voltage level and a third reference corresponding to a third voltage level. A second comparator has one of its inputs coupled to the memory cell and its second input is selectively coupled to either the second reference or the third reference.

Abstract: Bias selector circuitry for a memory cell sensing circuit is described. The bias selector circuitry includes a reference voltage generator, an output node, and a selector. The output node provides the bias voltage to the reference bitline load and the sense bitline load for controlling the reference and sense bitline node voltages, respectively. The selector provides a first bias voltage to the output node if a power supply voltage is at a first level. The selector selects the reference voltage generator to provide a second bias voltage to the output node if the power supply voltage is at a second level. The reference bitline node voltage is maintained at approximately the midpoint of the operating range of the sense bitline node voltage.