Abstract: An exemplary embodiment of the present disclosure provides a multiplexer/demultiplexer, comprising a plurality of unit cells arranged in a lattice, a first domain, a second domain, a third domain, and a controller. Each of the unit cells can comprise a topological-insulative material, a first piezoelectric patch, and a second piezoelectric patch. A first domain can comprise a first portion of the plurality of unit cells. A second domain can comprise a second portion of the plurality of unit cells. A third domain can comprise a third portion of the plurality of unit cells. The controller can be configured to: apply a negative capacitance to the first piezoelectric patches in the first domain; apply a negative capacitance to the second piezoelectric patches in the second domain; and alternately apply a negative capacitance to the first and second piezoelectric patches, respectively, in the third domain.

Abstract: An exemplary embodiment of the present disclosure provides a multiplexer/demultiplexer, comprising a plurality of unit cells arranged in a lattice, a first domain, a second domain, a third domain, and a controller. Each of the unit cells can comprise a topological-insulative material, a first piezoelectric patch, and a second piezoelectric patch. A first domain can comprise a first portion of the plurality of unit cells. A second domain can comprise a second portion of the plurality of unit cells. A third domain can comprise a third portion of the plurality of unit cells. The controller can be configured to: apply a negative capacitance to the first piezoelectric patches in the first domain; apply a negative capacitance to the second piezoelectric patches in the second domain; and alternately apply a negative capacitance to the first and second piezoelectric patches, respectively, in the third domain.