Abstract: A memory controller and methods for managing efficient writing to a flash memory are presented. Fresh data is written to at least one block of the flash memory. During a space reclamation process, other data, previously written to the flash memory, is relocated to at least one other block of the flash memory, such that the fresh data and the relocated data always are maintained in separate blocks of the flash memory. During writing, an update frequency level is selected for the fresh data from among multiple update frequency levels and the fresh data is written to a block that is associated with the selected update frequency level. During space reclamation, a plurality of blocks, space of which is to be reclaimed, is selected and the valid pages thereof are copied to at least one destination block.

Abstract: A memory controller and methods for managing efficient writing to a flash memory are presented. Fresh data is written to at least one block of the flash memory. During a space reclamation process, other data, previously written to the flash memory, is relocated to at least one other block of the flash memory, such that the fresh data and the relocated data always are maintained in separate blocks of the flash memory. During writing, an update frequency level is selected for the fresh data from among multiple update frequency levels and the fresh data is written to a block that is associated with the selected update frequency level. During space reclamation, a plurality of blocks, space of which is to be reclaimed, is selected and the valid pages thereof are copied to at least one destination block.

Abstract: A method of encoding and storing data. The method comprises providing digital data designated to be written in at least one memory element having a plurality of memory cells, encoding digital data so as to increase the prevalence of at least one memory cell state in relation to the prevalence of at least one other memory cell state by conditionally inverting the data bits in accordance with the count of a particular state in the data to be written, and programming the plurality of memory cells to store the encoded digital data.

Abstract: A method of managing a data storage medium. One portion of the medium is reserved for storing data files and directories. Another, separate portion of the medium is reserved for storing allocation information related to the data in the first portion. Upon beginning a change of one of the data files or directories in the first portion, that data file or directory is flagged robustly until the change is completed. As needed, for example when the medium is mounted on a host system, the incomplete changes to the flagged data files and directories are undone or completed.

Abstract: Cells of a flash memory are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their respective reference voltages. The adaptive reference voltages are determined either from analog measurements of the threshold voltages of the cells' neighbors or from preliminary estimates of the cells' threshold voltages based on comparisons of the cells' threshold voltages with integral or fractional reference voltages common to all the cells. Cells of a flash memory also are read by comparing the cells' threshold voltages to integral reference voltages, comparing the threshold voltages of cells that share a common bit pattern to a fractional reference voltage, and adjusting the reference voltages in accordance with the comparisons.

Abstract: Cells of a flash memory are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their respective reference voltages. The adaptive reference voltages are determined either from analog measurements of the threshold voltages of the cells' neighbors or from preliminary estimates of the cells' threshold voltages based on comparisons of the cells' threshold voltages with integral or fractional reference voltages common to all the cells. Cells of a flash memory also are read by comparing the cells' threshold voltages to integral reference voltages, comparing the threshold voltages of cells that share a common bit pattern to a fractional reference voltage, and adjusting the reference voltages in accordance with the comparisons.

Abstract: A data storage device includes a data storage medium, for example one or more flash memory modules, and a direct interface, to the data storage medium, that supports a file system protocol. Preferably, the data storable device also includes a physical communication interface such as a USB interface or a wireless interface, a user interface and a power source. The scope of the invention also includes appliances that include such data storage devices.

Abstract: Cells of a flash memory are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their respective reference voltages. The adaptive reference voltages are determined either from analog measurements of the threshold voltages of the cells' neighbors or from preliminary estimates of the cells' threshold voltages based on comparisons of the cells' threshold voltages with integral or fractional reference voltages common to all the cells. Cells of a flash memory also are read by comparing the cells' threshold voltages to integral reference voltages, comparing the threshold voltages of cells that share a common bit pattern to a fractional reference voltage, and adjusting the reference voltages in accordance with the comparisons.

Abstract: Cells of a flash memory are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their respective reference voltages. The adaptive reference voltages are determined either from analog measurements of the threshold voltages of the cells' neighbors or from preliminary estimates of the cells' threshold voltages based on comparisons of the cells' threshold voltages with integral or fractional reference voltages common to all the cells. Cells of a flash memory also are read by comparing the cells' threshold voltages to integral reference voltages, comparing the threshold voltages of cells that share a common bit pattern to a fractional reference voltage, and adjusting the reference voltages in accordance with the comparisons.

Abstract: Cells of a flash memory are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their respective reference voltages. The adaptive reference voltages are determined either from analog measurements of the threshold voltages of the cells' neighbors or from preliminary estimates of the cells' threshold voltages based on comparisons of the cells' threshold voltages with integral or fractional reference voltages common to all the cells. Cells of a flash memory also are read by comparing the cells' threshold voltages to integral reference voltages, comparing the threshold voltages of cells that share a common bit pattern to a fractional reference voltage, and adjusting the reference voltages in accordance with the comparisons.

Abstract: A method to personalize a computer environment of a computer system. The method includes storing at least a portion of a user profile in a portable storage medium, logging onto the computer system using a user identification and validating the user identification from a relevant user list by the computer system. The method also includes retrieving the portion from the portable storage medium and at least partially configuring the computer environment of the computer system according to the retrieved portion, by the computer system. A method is also included to provide personalized services to a user. This method includes storing at least a portion of a user profile in a portable storage medium and retrieving the portion from the portable storage medium by a web server. This method additionally includes at least partially configuring an Internet service according to the retrieved portion by said web server.

Abstract: A data storage and processing device is reversibly attachable to a selected member of a set of appliances. The device includes a data storage medium and a processor. Each appliance includes appropriate functional components, a power source and a user interface. The device receives power from the attached appliance. Commands for operating the attached appliance are stored in the data storage medium and are executed by the processor in response to user instructions received from the attached appliance in order to operate the functional components. Preferably, the device receives power only from the attached appliance, and the functional components are operated, in response to the user instructions, only by the device's processor.

Abstract: A system and method for enabling concurrent usage of non-volatile memory for code execution and data storage/processing, comprising a hardware mechanism that can support automatic suspend and resume operations. This mechanism entails the integration of a suspend logic circuit and a resume logic circuit into the chip hardware, or the stationing of the logic chip in any way that it can operate together with the chip. This system and method enable a Flash memory chip to process code execution while it is processing erase/program operations, avoiding conflicts that ordinarily crash such a system. This is achieved by sensing the operation status of the chip and the CPU/Bus activity, and commanding the flash memory device to suspend and/or resume program/erase operations at appropriate times, so as not to conflict with read requests.

Abstract: A multi-level flash memory cell is read by comparing the cell's threshold voltage to a plurality of integral reference voltages and to a fractional reference voltage. Multi-level cells of a flash memory are programmed collectively with data and redundancy bits at each significance level, preferably with different numbers of data and redundancy bits at each significance level. The cells are read collectively, from lowest to highest significance level, by correcting the bits at each significance level according to the redundancy bits and adjusting the bits of the higher significance levels accordingly. The adjustment following the correction of the least significant bits is in accordance with comparisons of a cell's threshold voltages to fractional reference voltages.

Abstract: Cells of a flash memory are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their respective reference voltages. The adaptive reference voltages are determined either from analog measurements of the threshold voltages of the cells' neighbors or from preliminary estimates of the cells' threshold voltages based on comparisons of the cells' threshold voltages with integral or fractional reference voltages common to all the cells. Cells of a flash memory also are read by comparing the cells' threshold voltages to integral reference voltages, comparing the threshold voltages of cells that share a common bit pattern to a fractional reference voltage, and adjusting the reference voltages in accordance with the comparisons.

Abstract: A multi-level flash memory cell is read by comparing the cell's threshold voltage to a plurality of integral reference voltages and to a fractional reference voltage. Multi-level cells of a flash memory are programmed collectively with data and redundancy bits at each significance level, preferably with different numbers of data and redundancy bits at each significance level. The cells are read collectively, from lowest to highest significance level, by correcting the bits at each significance level according to the redundancy bits and adjusting the bits of the higher significance levels accordingly. The adjustment following the correction of the least significant bits is in accordance with comparisons of a cell's threshold voltages to fractional reference voltages.

Abstract: A storage unit made of flash array and a USB controller, is implemented to be compatible with then the USB specification. The unit includes memory modules which can accept write commands and read commands and are erasable and non-volatile herein referred to as flash modules. The USB/flash controller is configured to provide USB functionality and compatibility alone along with common flash operations such as programming reading and erasing the above mentioned components.

Abstract: A storage unit made of flash array and a USB controller, is implemented to be compatible with then the USB specification. The unit includes memory modules which can accept write commands and read commands and are erasable and non-volatile herein referred to as flash modules. The USB/flash controller is configured to provide USB functionality and compatibility alone along with common flash operations such as programming reading and erasing the above mentioned components.

Abstract: A storage unit made of flash array and a USB controller, is implemented to be compatible with then USB specification. The unit includes memory modules which can accept write commands and read commands and are erasable and non-volatile herein referred to as flash modules. The USB/flash controller is configured to provide USB functionality and compatibility alone with common flash operations such as programming reading and erasing the above mentioned components. A USB flash memory device includes at least one flash memory module, a USB connector, a USB controller, and an identification structure for holding memory size and manufacturing type information of the flash memory module.

Abstract: A storage unit made of flash array and a USB controller, is implemented to be compatible with then USB specification. The unit includes memory modules which can accept write commands and read commands and are erasable and non-volatile herein referred to as flash modules. The USB/flash controller is configured to provide USB functionality and compatibility alone with common flash operations such as programming reading and erasing the above mentioned components. A USB flash memory device includes at least one flash memory module, a USB connector, a USB controller, and an identification structure for holding memory size and manufacturing type information of the flash memory module.