Abstract: A packet received via a network is stored in a packet memory. Information in a header of the packet is analyzed to determine multiple ports to which the packet is to be forwarded. The packet is read from the packet memory in connection with transmitting the packet via a first port among the multiple ports. Packet data corresponding to the packet is stored in a packet cache different than the packet memory. In connection with forwarding one or more instances of the packet to ports among the multiple ports, the packet data is read, based on information included in a packet descriptor associated with the packet, from the packet cache. Ones of the one or more instances of the packet are forwarded, using the data corresponding to the packet read from the packet cache and without further accessing the packet memory, to respective one or more of the multiple ports.

Abstract: Aspects of the disclosure provide a circuit that includes a plurality of memory access circuits configured to access a memory to read or write data of a first width. The memory includes a plurality of memory banks that are organized in hierarchy. Further, the circuit includes a plurality of interface circuits respectively associated with the plurality of memory access circuits. Each interface circuit is configured to receive memory access requests to first level memory banks from an associated memory access circuit, segment the memory access requests into sub-requests to corresponding second level memory banks, buffer the sub-requests into buffers associated with the second level memory banks. In addition, the circuit includes arbitration circuitry configured to control multiplexing paths from the buffers to the second level memory banks to enable, in a same memory access clock, memory accesses by the memory access circuits.

Abstract: A packet received via a network is stored in a packet memory. Information in a header of the packet is analyzed to determine one or more ports to which the packet is to be forwarded. The packet is read from the packet memory. It is ascertained whether the packet is of a multicast-type. In response to determining that the packet is the multicast-type, packet data that is i) read from the packet memory and ii) corresponds to the packet, is stored in a packet cache; the packet data is read from the packet cache, and multiple instances of the packet are forwarded to appropriate ports without further accessing the packet memory.

Abstract: A network device which controls the flow of packets from a best-effort client is provided. The network device includes a flow controller which transmits transaction messages between the best effort client and an arbiter, and an average rate monitor which comprises a counter which increments at an amount of (x?1) when a transaction occurrence is detected by the average rate monitor, and decrements at an amount of 1 per cycle when a transaction occurrence is not detected by the average rate monitor. The best-effort client is only given a grant by the arbiter when the counter has a value of zero.