Abstract: A method for generating a set of analytical redundancy relations representative of a system with which a plurality of sensors is associated for the observation of variables indicative of operating conditions and adapted to enable detection and discrimination of faults. A complete set of analytical redundancy relations of the system is built from a set of intermediate relations established between observable and non-observable variables of the system, wherein each intermediate relation is generated by combining two predetermined relations Rj, Rk, each of which is expressed in an implicit form as a tuple (i) of a subset Sj of system variables, (ii) of the set Cj of the support components for said relation, and (iii) of the set Tj of the primary relations used to derive said intermediate relation.

Abstract: A method for generating a minimal set of Analytical Redundancy Relations representing a system to which a plurality of sensors is associated for the observation of variables indicative of operating conditions and adapted to enable detection and isolation of faults. The minimal set of Analytical Redundancy Relations is derived from a complete set of Analytical Redundancy Relations in implicit form, for which an associated binary Fault Signature Matrix is specified, and comprises the relations associated to a minimal subset of rows of the original matrix, which has the same number of non-zero columns and the same number of distinct columns as the original matrix.

Abstract: A method for the generation of a set of conflicts for model-based system diagnostics is described, with which system a plurality of sensors is associated for the observation of variables indicative of operation conditions. The method starts from generating a complete set of Analytical Redundancy Relations (ARRs) in implicit form and, for each diagnosis instance: it performs a system simulation, computing the expected values for a first subset of Analytical Redundancy Relations (D-ARRs) including the relations involving only one system observation variable; it compares the expected and observed values of the system observation variables to identify the inconsistent variables, i.e.

Abstract: A method is described for generating a minimal set of Analytical Redundancy Relations representing a system to which a plurality of sensors is associated for the observation of variables indicative of operating conditions and adapted to enable detection and isolation of faults. The minimal set of Analytical Redundancy Relations is derived from a complete set of Analytical Redundancy Relations in implicit form, for which an associated binary Fault Signature Matrix is specified, and comprises the relations associated to a minimal subset of rows of the original matrix, which has the same number of non-zero columns and the same number of distinct columns as the original matrix.

Abstract: A method for the generation of a set of conflicts for model-based system diagnostics is described, with which system a plurality of sensors is associated for the observation of variables indicative of operation conditions. The method starts from generating a complete set of Analytical Redundancy Relations (ARRs) in implicit form and, for each diagnosis instance: it performs a system simulation, computing the expected values for a first subset of Analytical Redundancy Relations (D-ARRs) including the relations involving only one system observation variable; it compares the expected and observed values of the system observation variables to identify the inconsistent variables, i.e.

Abstract: A method is described for generating a set of analytical redundancy relations representative of a system with which a plurality of sensors is associated for the observation of variables indicative of operating conditions and adapted to enable detection and discrimination of faults.

Abstract: An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Abstract: The diagnosis problem arises when a system's actual behavior contradicts the expected behavior, thereby exhibiting symptoms (a collection of conflict sets). System diagnosis is then the task of identifying faulty components that are responsible for anomalous behavior. To solve the diagnosis problem, the present invention describes a method for finding the minimal set of faulty components (minimal diagnosis set) that explain the conflict sets. The method includes acts of creating a matrix of the collection of conflict sets, and then creating nodes from the matrix such that each node is a node in a search tree. A determination is made as to whether each node is a leaf node or has any children nodes. If any given node has children nodes, then the node is split until all nodes are leaf nodes. Information gathered from the leaf nodes is used to determine the minimal diagnosis set.

Abstract: An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Abstract: The diagnosis problem arises when a system's actual behavior contradicts the expected behavior, thereby exhibiting symptoms (a collection of conflict sets). System diagnosis is then the task of identifying faulty components that are responsible for anomalous behavior. To solve the diagnosis problem, the present invention describes a method for finding the minimal set of faulty components (minimal diagnosis set) that explain the conflict sets. The method includes acts of creating a matrix of the collection of conflict sets, and then creating nodes from the matrix such that each node is a node in a search tree. A determination is made as to whether each node is a leaf node or has any children nodes. If any given node has children nodes, then the node is split until all nodes are leaf nodes. Information gathered from the leaf nodes is used to determine the minimal diagnosis set.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: The present invention enhances the bit resolution of a CCD/CID MVM processor by storing each bit of each matrix element as a separate CCD charge packet. The bits of each input vector are separately multiplied by each bit of each matrix element in massive parallelism and the resulting products are combined appropriately to synthesize the correct product. In another aspect of the invention, such arrays are employed in a pseudo-spectral method of the invention, in which partial differential equations are solved by expressing each derivative analytically as matrices, and the state function is updated at each computation cycle by multiplying it by the matrices. The matrices are treated as synaptic arrays of a neural network and the state function vector elements are treated as neurons. In a further aspect of the invention, moving target detection is performed by driving the soliton equation with a vector of detector outputs.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: The present invention discloses increased bit resolution of a charge coupled device (CCD)/charge injection device (CID) matrix vector multiplication (MVM) processor by storing each bit of each matrix element as a separate CCD charge packet. The bits of each input vector are separately multiplied by each bit of each matrix element in massive parallelism and the resulting products are combined appropriately to synthesize the correct product. In addition, such arrays are employed in a pseudo-spectral method of the invention, in which partial differential equations are solved by expressing each derivative analytically as matrices, and the state function is updated at each computation cycle by multiplying it by the matrices. The matrices are treated as synaptic arrays of a neutral network and the state function vector elements are treated as neurons. Further, moving target detection is performed by driving the soliton equation with a vector of detector outputs.

Abstract: In a computer having a large number of single-instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master control unit and interconnected among a plurality of register file units where data is stored. The register files input and output data in synchronism with a minor cycle clock under control of two slave control units controlling the register file units connected to respective ones of the two sets of processor elements. Depending upon which ones of the register file units are enabled to store or transmit data during a particular minor clock cycle, the processor elements within an SIMD processor are connected in rings or in pipeline arrays, and may exchange data with the internal bus or with neighboring SIMD processors through interface units controlled by respective ones of the two slave control units.

Abstract: A Real-time Robotic Controller and Simulator (RRCS) with an MIMD-SIMD parallel architecture for interfacing with an external host computer provides a high degree of parallelism in computation for robotics control and simulation. A host processor receives instructions from, and transmits answers to, the external host computer. A plurality of SIMD microprocessors, each SIMD processor being an SIMD parallel processor, is capable of exploiting fine-grain parallelism and is able to operate asynchronously to form an MIMD architecture. Each SIMD processor comprises an SIMD architecture capable of performing two matrix-vector operations in parallel while fully exploiting parallelism in each operation. A system bus connects the host processor to the plurality of SIMD microprocessors and a common clock provides a continuous sequence of clock pulses.