Patents by Inventor Amir H. Farrahi

Amir H. Farrahi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7469395
    Abstract: An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability ?SD per clock cycle that is no less than a pre-selected minimum same-direction switching probability ?SD,MIN or has an opposite-direction switching probability ?OD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability ?OD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: December 23, 2008
    Assignee: International Business Machines Corporation
    Inventors: John M. Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas M. Lepsic, Jagannathan Narasimhan, Scott A. Tetreault, Sebastian T. Ventrone
  • Patent number: 7370305
    Abstract: One embodiment of the present invention provides a system that determines a feasible cell placement for an integrated circuit design. During operation, the system receives an input cell placement, which is typically determined using a quadratic placement technique. Next, the system receives a set of regions within the integrated circuit design. Each region has a capacity constraint which specifies an upper limit on the total cell area that can be placed within the region. The system then generates a bi-partite graph which comprises instance vertices, region vertices, and edges. An instance vertex is associated with a cell instance, a region vertex is associated with a region, and each edge is incident on an instance vertex and a region vertex. Each edge is assigned a cost that indicates the cost of placing the associated cell instance in the associated region. Next, the system associates edges with shadow edges. Note that an edge and an associated shadow edge are incident to the same instance vertex.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: May 6, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Amir H. Farrahi, Anurag Bhatnagar, Nabanjan Das
  • Patent number: 7346875
    Abstract: An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: March 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: John M. Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas M. Lepsic, Jagannathan Narasimhan, Scott A. Tetreault, Sebastian T. Ventrone
  • Patent number: 7135907
    Abstract: A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: November 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Anthony Richard Bonaccio, John Maxwell Cohn, Alvar Antonio Dean, Amir H. Farrahi, David J. Hathaway, Sebastian Theodore Ventrone
  • Patent number: 7071757
    Abstract: A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: July 4, 2006
    Assignee: International Business Machines Corporation
    Inventors: Anthony Richard Bonaccio, John Maxwell Cohn, Alvar Antonio Dean, Amir H. Farrahi, David J. Hathaway, Sebastian Theodore Ventrone
  • Patent number: 6985004
    Abstract: An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: John M. Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas M. Lepsic, Jagannathan Narasimhan, Scott A. Tetreault, Sebastian T. Ventrone
  • Patent number: 6711719
    Abstract: In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: March 23, 2004
    Assignee: International Business Machines Corporation
    Inventors: John Maxwell Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas Michael Lepsic, Patrick Edward Perry, Scott A. Tetreault, Sebastian T. Ventrone
  • Publication number: 20030158714
    Abstract: An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.
    Type: Application
    Filed: February 12, 2001
    Publication date: August 21, 2003
    Inventors: John M. Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas M. Lepsic, Jagannathan Narasimhan, Scott A. Tetreault, Sebastian T. Ventrone
  • Publication number: 20030042962
    Abstract: A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.
    Type: Application
    Filed: September 6, 2001
    Publication date: March 6, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony Richard Bonaccio, John Maxwell Cohn, Alvar Antonio Dean, Amir H. Farrahi, David J. Hathaway, Sebastian Theodore Ventrone
  • Publication number: 20030033580
    Abstract: In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.
    Type: Application
    Filed: August 13, 2001
    Publication date: February 13, 2003
    Applicant: International Business Machines Corporation
    Inventors: John Maxwell Cohn, Alvar A. Dean, Amir H. Farrahi, David J. Hathaway, Thomas Michael Lepsic, Patrick Edward Perry, Scott A. Tetreault, Sebastian T. Ventrone