Abstract: Systems and methods are provided for handling jitter improvement in transmitters. During processing of input data for serial transmission, it may be determined if jitter may occur, and when jitter occurs one or more adjustments may be determined, based on dummy data, to reduce jitter in an output corresponding to the input data. The one or more adjustments may then be applied during processing of the input data, to reduce jitter in a serial output corresponding to the input data. The dummy data may be generated based on the input data. The dummy data may be configured such that it may generate corresponding dummy current pulses which may be used in controlling supply variations during generation of the serial output. The use of the dummy data may be selectively turned on or off.

Abstract: According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.

Abstract: Systems and methods are provided for handling jitter improvement in transmitters. During processing of input data for serial transmission, it may be determined if jitter may occur, and when jitter occurs one or more adjustments may be determined, based on dummy data, to reduce jitter in an output corresponding to the input data. The one or more adjustments may then be applied during processing of the input data, to reduce jitter in a serial output corresponding to the input data. The dummy data may be generated based on the input data. The dummy data may be configured such that it may generate corresponding dummy current pulses which may be used in controlling supply variations during generation of the serial output. The use of the dummy data may be selectively turned on or off.

Abstract: Systems and methods are provided for jitter improvement in serializer-deserializer (SerDes) transmitters. One or more adjustments may be applied in SerDes transmitter circuitry to reduce jitter in a serial output of the SerDes transmitter circuitry, which may occur as a result of processing of input data. Applying the one or more adjustments may comprise use of dummy data. The dummy data may be configured to generate corresponding dummy current pulses which may in turn be used in controlling supply variations occurring during processing of the input data and/or generation of the serial output. The dummy data may be configured to generate the dummy current pulses such that they are applied along with current pulses corresponding to the input data. The dummy data may be adaptively set or adjusted based on the input data. The use of the dummy data may be selectively turned on or off.

Abstract: A single hybrid receiver is provided for processing both single carrier and carrier aggregated (CA) communications signals where carriers are split into independent receive paths without any additional external components. The receiver receives all contiguous and non-contiguous intra-band CA and inter-band CA signals, including those of unequal bandwidths, allowing for improved rejection and balanced rejection of jamming signals on either side of the two carrier signals.

Abstract: Systems and methods are provided for jitter improvement in serializer-deserializer (SerDes) transmitters. One or more adjustments may be applied in SerDes transmitter circuitry to reduce jitter in a serial output of the SerDes transmitter circuitry, which may occur as a result of processing of input data. Applying the one or more adjustments may comprise use of dummy data. The dummy data may be configured to generate corresponding dummy current pulses which may in turn be used in controlling supply variations occurring during processing of the input data and/or generation of the serial output. The dummy data may be configured to generate the dummy current pulses such that they are applied along with current pulses corresponding to the input data. The dummy data may be adaptively set or adjusted based on the input data. The use of the dummy data may be selectively turned on or off.

Abstract: A single hybrid receiver is provided for processing both single carrier and carrier aggregated (CA) communications signals where carriers are split into independent receive paths without any additional external components. The receiver receives all contiguous and non-contiguous intra-band CA and inter-band CA signals, including those of unequal bandwidths, allowing for improved rejection and balanced rejection of jamming signals on either side of the two carrier signals.

Abstract: A single hybrid receiver is provided for processing both single carrier and carrier aggregated (CA) communications signals where carriers are split into independent receive paths without any additional external components. The receiver receives all contiguous and non-contiguous intra-band CA and inter-band CA signals allowing for improved rejection and balanced rejection of jamming signals on either side of the two carrier signals.

Abstract: An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED.

Abstract: A circuit for a low-noise interface between an amplifier and an analog-to-digital converter (ADC) may comprise a capacitor element having a capacitance of C coupled between a first and second output node of the amplifier. A resistor circuit coupled between the capacitor element and input nodes of the ADC. A desired value RL for a load resistance of the amplifier is provided by selecting suitable initial values for resistances of the resistor circuit. A desired bandwidth for the at least one amplifier is achieved by selecting a value of the capacitance C based on the desired value RL for the load resistance.

Abstract: According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.

Abstract: A circuit for a low-noise interface between an amplifier and an analog-to-digital converter (ADC) may comprise a capacitor element having a capacitance of C coupled between a first and second output node of the amplifier. A resistor circuit coupled between the capacitor element and input nodes of the ADC. A desired value RL for a load resistance of the amplifier is provided by selecting suitable initial values for resistances of the resistor circuit. A desired bandwidth for the at least one amplifier is achieved by selecting a value of the capacitance C based on the desired value RL for the load resistance.

Abstract: According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.

Abstract: A single hybrid receiver is provided for processing both single carrier and carrier aggregated (CA) communications signals where carriers are split into independent receive paths without any additional external components. The receiver receives all contiguous and non-contiguous intra-band CA and inter-band CA signals allowing for improved rejection and balanced rejection of jamming signals on either side of the two carrier signals.

Abstract: A circuit for a low-noise interface between an amplifier and an analog-to-digital converter (ADC) may comprise a capacitor element having a capacitance of C coupled between a first and second output node of the amplifier. A first resistor R1 may be coupled in parallel with the capacitor. A second resistor R2 may be coupled between the first output node of the amplifier and a first input node of the ADC. A third resistor R3 may be coupled between the second output node of the amplifier and a second input node of the ADC. Initial values of the resistances R1, R2, and R3 may be selected to provide a desired value RL for a load resistance of the amplifier. A value of the capacitance C may be selected so that, in combination with the desired value RL, a desired bandwidth for the amplifier is achieved.

Abstract: An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of a radio frequency (RF) signal input, the RF signal input including an output of a radio such as a cellular transmitter (TX). The ED further includes multiple voltage amplifiers positioned serially in gain stages between the TX output and the ED core to provide a total linear voltage range of the envelope detector. A final voltage amplifier of the multiple voltage amplifiers drives the ED core and includes a class-AB RF amplifier configured to operate within a full linear voltage range of the ED core.

Abstract: According to one embodiment, a high performance buffer for use in a communications system includes first and second differential blocks. Each of the first and second differential blocks comprise one or more driving transistors for generating a driving current for a load of the high performance buffer, and a feedback path for adjusting the operation of the one or more driving transistors. The feedback path includes a feedback transistor for receiving a common mode bias voltage, wherein the common mode bias voltage depends at least in part on a threshold voltage of the feedback transistor. The feedback path includes a programmable resistor and capacitor to reduce out of band loop gain and the noise. The high performance buffer is configured to achieve a high linearity, low output impedance, and low noise, and is suitable for use as a pre-mixer buffer in a wireless communications system.

Abstract: A circuit for a low-noise interface between an amplifier and an analog-to-digital converter (ADC) may comprise a capacitor element having a capacitance of C coupled between a first and second output node of the amplifier. A first resistor R1 may be coupled in parallel with the capacitor. A second resistor R2 may be coupled between the first output node of the amplifier and a first input node of the ADC. A third resistor R3 may be coupled between the second output node of the amplifier and a second input node of the ADC. Initial values of the resistances R1, R2, and R3 may be selected to provide a desired value RL for a load resistance of the amplifier. A value of the capacitance C may be selected so that, in combination with the desired value RL, a desired bandwidth for the amplifier is achieved.

Abstract: An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED.

Abstract: An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of a radio frequency (RF) signal input, the RF signal input including an output of a radio such as a cellular transmitter (TX). The ED further includes multiple voltage amplifiers positioned serially in gain stages between the TX output and the ED core to provide a total linear voltage range of the envelope detector. A final voltage amplifier of the multiple voltage amplifiers drives the ED core and includes a class-AB RF amplifier configured to operate within a full linear voltage range of the ED core.