Abstract: A clock generator for providing a desired system clock signal in accordance with an embodiment of the present application includes a ring oscillator operable to provide an oscillator output signal having a first frequency, a divider operable to divide the oscillator output signal by a predetermined divisor and to output the divided signal as the desired system clock signal, a reference device operable to provide a reference signal with a known second frequency and a ratio device operable to provide a ratio value indicative of a relationship between the oscillator output signal and the reference signal, wherein the predetermined divisor of the divider is determined based on the ratio value such that the desired system clock signal has a desired frequency.

Abstract: A system and method for improved synchronous access of stored data are provided herein. A data requestor transmits a clock signal and a read request signal for reception by a data source, whereupon skewed versions of the clock signal and the read request signal are received due to the delays in the signal paths between the data requestor and the data source. Accordingly, the data requestor provides skewed clock and read request signals to its input sampling module to simulate the delays of the signal paths. Additionally, the data requestor provides process information associated with the requested data to a dual clock first in-first out (FIFO) buffer. When the input sampling module detects a read request using the skewed read request signal, the input sampling module can use this signal and the skewed clock signal to sample a data signal from the data source to obtain the requested data.

Abstract: A system and method for improved synchronous access of stored data are provided herein. A data requestor transmits a clock signal and a read request signal for reception by a data source, whereupon skewed versions of the clock signal and the read request signal are received due to the delays in the signal paths between the data requestor and the data source. Accordingly, the data requestor provides skewed clock and read request signals to its input sampling module to simulate the delays of the signal paths. Additionally, the data requestor provides process information associated with the requested data to a dual clock first in-first out (FIFO) buffer. When the input sampling module detects a read request using the skewed read request signal, the input sampling module can use this signal and the skewed clock signal to sample a data signal from the data source to obtain the requested data.

Abstract: A chip select circuit is based on a multiplexed bus having a chip select phase, an address phase, and a data phase. During the chip select phase, a chip select latch receives chip select signals from the multiplexed bus at one input and a chip select enable signal at a second input. The chip select latch has a plurality of outputs to the chip select inputs of a plurality of connected devices. Based on the chip select signals from the multiplexed bus, one of the plurality of outputs enables a selected connected device. During the address phase, an address latch receives address signals from the multiplexed bus at a first input and an address enable signal at a second inputs. The output of the address latch passes the address signals to the address inputs of the plurality of connected devices. The chip select circuit is operative to used the multiplexed bus to select one of the connected devices using the single chip select enable signal without requiring further enabling/control signals.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.