Patents by Inventor Amir Hossein Atabaki
Amir Hossein Atabaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10768368Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer.Type: GrantFiled: November 12, 2019Date of Patent: September 8, 2020Assignee: Massachusetts Institute of TechnologyInventors: Jason Scott Orcutt, Karan Kartik Mehta, Rajeev Jagga Ram, Amir Hossein Atabaki
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Publication number: 20200081184Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer.Type: ApplicationFiled: November 12, 2019Publication date: March 12, 2020Inventors: Jason Scott ORCUTT, Karan Kartik MEHTA, Rajeev Jagga Ram, Amir Hossein ATABAKI
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Patent number: 10514504Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer.Type: GrantFiled: February 22, 2018Date of Patent: December 24, 2019Assignee: Massachusetts Institute of TechnologyInventors: Jason Scott Orcutt, Karan Kartik Mehta, Rajeev Jagga Ram, Amir Hossein Atabaki
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Publication number: 20180180811Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer.Type: ApplicationFiled: February 22, 2018Publication date: June 28, 2018Inventors: Jason Scott Orcutt, Karan Kartik Mehta, Rajeev Jagga Ram, Amir Hossein Atabaki
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Patent number: 9946022Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer.Type: GrantFiled: November 30, 2016Date of Patent: April 17, 2018Inventors: Jason Scott Orcutt, Karan Kartik Mehta, Rajeev Jagga Ram, Amir Hossein Atabaki
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Publication number: 20170146740Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer.Type: ApplicationFiled: November 30, 2016Publication date: May 25, 2017Applicant: Massachusetts Institute of TechnologyInventors: Jason Scott Orcutt, Karan Kartik Mehta, Rajeev Jagga Ram, Amir Hossein Atabaki
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Patent number: 9529150Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer.Type: GrantFiled: October 22, 2014Date of Patent: December 27, 2016Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Jason Scott Orcutt, Karan Kartik Mehta, Rajeev Jagga Ram, Amir Hossein Atabaki
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Publication number: 20150125111Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer.Type: ApplicationFiled: October 22, 2014Publication date: May 7, 2015Applicant: Massachusetts Institute of TechnologyInventors: Jason Scott Orcutt, Karan Kartik Mehta, Rajeev Jagga Ram, Amir Hossein Atabaki