Patents by Inventor Amir JAVIDI

Amir JAVIDI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • AREA-EFFICIENT SCALABLE MEMORY READ-DATA MULTIPLEXING AND LATCHING
    Publication number: 20230137508
    Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 4, 2023
    Inventors: Amir JAVIDI, Daniel CUMMINGS, Glenn STARNES
  • Area-efficient scalable memory read-data multiplexing and latching
    Patent number: 11619963
    Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Amir Javidi, Daniel Cummings, Glenn Starnes
  • AREA-EFFICIENT SCALABLE MEMORY READ-DATA MULTIPLEXING AND LATCHING
    Publication number: 20210294374
    Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Applicant: Intel Corporation
    Inventors: Amir JAVIDI, Daniel CUMMINGS, Glenn STARNES
  • Area-efficient scalable memory read-data multiplexing and latching
    Patent number: 11029720
    Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Amir Javidi, Daniel Cummings, Glenn Starnes
  • AREA-EFFICIENT SCALABLE MEMORY READ-DATA MULTIPLEXING AND LATCHING
    Publication number: 20200333825
    Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.
    Type: Application
    Filed: April 16, 2019
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Amir JAVIDI, Daniel CUMMINGS, Glenn STARNES