Patents by Inventor Amir Laufer
Amir Laufer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240020256Abstract: Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.Type: ApplicationFiled: September 29, 2023Publication date: January 18, 2024Applicant: Intel CorporationInventors: Kevan A. Lillie, Shlomi Lalush, Yaakov Dalsace, Adee Ofir Ran, Assaf Benhamou, David Golodni, Itay Tamir, Amir Laufer
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Patent number: 11809353Abstract: Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.Type: GrantFiled: March 31, 2017Date of Patent: November 7, 2023Assignee: INTEL CORPORATIONInventors: Kevan A. Lillie, Shlomi Lalush, Yaakov Dalsace, Adee Ofir Ran, Assaf Benhamou, David Golodni, Itay Tamir, Amir Laufer
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Publication number: 20220200712Abstract: Examples described herein relate to a physical layer interface (PHY) that includes circuitry configured to autonomously measure for signal degradation by a baseline measurement of parameters and one or more subsequent measurements of parameters to indicate if link loss is expected.Type: ApplicationFiled: March 8, 2022Publication date: June 23, 2022Inventors: Andrew K. LILLIE, Itamar LEVIN, Amir LAUFER
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Patent number: 10797855Abstract: Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.Type: GrantFiled: July 16, 2018Date of Patent: October 6, 2020Assignee: INTEL CORPORATIONInventors: Amir Laufer, Itamar Levin, Kevan A. Lillie
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Publication number: 20190173664Abstract: Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.Type: ApplicationFiled: July 16, 2018Publication date: June 6, 2019Applicant: INTEL CORPORATIONInventors: AMIR LAUFER, ITAMAR LEVIN, KEVAN A. LILLIE
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Publication number: 20180285298Abstract: Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: KEVAN A. LILLIE, SHLOMI LALUSH, YAAKOV DALSACE, ADEE OFIR RAN, ASSAF BENHAMOU, DAVID GOLODNI, ITAY TAMIR, AMIR LAUFER
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Patent number: 10027470Abstract: Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.Type: GrantFiled: December 28, 2016Date of Patent: July 17, 2018Assignee: INTEL CORPORATIONInventors: Amir Laufer, Itamar Levin, Kevan A. Lillie
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Publication number: 20180183568Abstract: Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.Type: ApplicationFiled: December 28, 2016Publication date: June 28, 2018Applicant: INTEL CORPORATIONInventors: AMIR LAUFER, ITAMAR LEVIN, KEVAN A. LILLIE
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Patent number: 9917685Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: GrantFiled: June 5, 2017Date of Patent: March 13, 2018Assignee: INTEL CORPORATIONInventors: Dima Hammad, Vadim Levin, Amir Laufer, Ron Bar-Lev, Noam Familia, Itamar Levin
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Publication number: 20170279592Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: ApplicationFiled: June 5, 2017Publication date: September 28, 2017Applicant: Intel CorporationInventors: DIMA HAMMAD, VADIM LEVIN, AMIR LAUFER, RON BAR-LEV, NOAM FAMILIA, ITAMAR LEVIN
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Patent number: 9680668Abstract: Described is an apparatus which comprises a decision feedback equalizer (DFE) having a first DFE tap path and non-first DFE tap paths, wherein the DFE includes a variable delay circuit in a signal path of the non-first DFE tap paths. In some embodiment, an apparatus is provided which comprises: a summer; a slicer to receive input from the summer; a first feedback loop to cancel a first post-cursor, the first feedback loop forming a loop by coupling the slicer to the summer; and a second feedback loop to cancel a second post-cursor, the second feedback loop forming a loop by coupling an input of the first feedback loop to the summer, wherein the second feedback loop having a programmable delay at its input.Type: GrantFiled: December 16, 2014Date of Patent: June 13, 2017Assignee: Intel CorporationInventors: Amir Laufer, Itamar Levin
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Patent number: 9673966Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: GrantFiled: December 14, 2015Date of Patent: June 6, 2017Assignee: INTEL CORPORATIONInventors: Dima Hammad, Vadim Levin, Amir Laufer, Ron Bar-Lev, Noam Familia, Itamar Levin
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Publication number: 20160211965Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: ApplicationFiled: December 14, 2015Publication date: July 21, 2016Applicant: Intel CorporationInventors: DIMA HAMMAD, VADIM LEVIN, AMIR LAUFER, RON BAR-LEV, NOAM FAMILIA, ITAMAR LEVIN
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Publication number: 20160173300Abstract: Described is an apparatus which comprises a decision feedback equalizer (DFE) having a first DFE tap path and non-first DFE tap paths, wherein the DFE includes a variable delay circuit in a signal path of the non-first DFE tap paths. In some embodiment, an apparatus is provided which comprises: a summer; a slicer to receive input from the summer; a first feedback loop to cancel a first post-cursor, the first feedback loop forming a loop by coupling the slicer to the summer; and a second feedback loop to cancel a second post-cursor, the second feedback loop forming a loop by coupling an input of the first feedback loop to the summer, wherein the second feedback loop having a programmable delay at its input.Type: ApplicationFiled: December 16, 2014Publication date: June 16, 2016Inventors: Amir Laufer, Itamar Levin
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Patent number: 9215061Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: GrantFiled: March 24, 2015Date of Patent: December 15, 2015Assignee: Intel CorporationInventors: Dima Hammad, Vadim Levin, Amir Laufer, Ron Bar-Lev, Noam Familia, Itamar Levin
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Publication number: 20150200767Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: ApplicationFiled: March 24, 2015Publication date: July 16, 2015Applicant: Intel CorporationInventors: DIMA HAMMAD, VADIM LEVIN, AMIR LAUFER, RON BAR-LEV, NOAM FAMILIA, ITAMAR LEVIN
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Patent number: 8989329Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: GrantFiled: March 15, 2013Date of Patent: March 24, 2015Assignee: Intel CorporationInventors: Dima Hammad, Vadim Levin, Amir Laufer, Ron Bar-Lev, Noam Familia, Itamar Levin
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Publication number: 20140270030Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: DIMA HAMMAD, VADIM LEVIN, AMIR LAUFER, RON BAR-LEV, NOAM FAMILIA, ITAMAR LEVIN
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Patent number: 8576896Abstract: Implementations of improved OSTC decoding are disclosed where received channel output corresponding to a partial OSTC codeword may be used to generate estimated channel output, and where the received channel output and the estimated channel output may be used to reconstruct the OSTC codeword.Type: GrantFiled: February 4, 2009Date of Patent: November 5, 2013Assignee: New Jersey Institute Of TechnologyInventors: Yeheskel Bar-Ness, Amir Laufer
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Patent number: 8379746Abstract: Implementations of improved transmission of orthogonal space time codes are disclosed.Type: GrantFiled: February 4, 2009Date of Patent: February 19, 2013Inventors: Yeheskel Bar-Ness, Amir Laufer