Patents by Inventor Amir Lehavot
Amir Lehavot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8165112Abstract: Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.Type: GrantFiled: February 9, 2009Date of Patent: April 24, 2012Assignee: Tellabs San Jose, Inc.Inventors: Raghavan Menon, Adam Goldstein, Mark D. Griswold, Mitri I. Halabi, Mohammad K. Issa, Amir Lehavot, Shaham Parvin, Xiaoyang Zheng
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Patent number: 8104001Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.Type: GrantFiled: October 31, 2008Date of Patent: January 24, 2012Assignee: Cadence Design Systems, Inc.Inventors: Amir Lehavot, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer
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Patent number: 8099695Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.Type: GrantFiled: August 2, 2006Date of Patent: January 17, 2012Assignee: Cadence Design Systems, Inc.Inventors: Amir Lehavot, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer
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Patent number: 8099696Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.Type: GrantFiled: October 31, 2008Date of Patent: January 17, 2012Assignee: Cadence Design Systems, Inc.Inventors: Amir Lehavot, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer
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Patent number: 7984401Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.Type: GrantFiled: October 31, 2008Date of Patent: July 19, 2011Assignee: Cadence Design Systems, Inc.Inventors: Amir Lehavot, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer
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Publication number: 20090201923Abstract: Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.Type: ApplicationFiled: February 9, 2009Publication date: August 13, 2009Applicant: TELLABS SAN JOSE, INC.Inventors: RAGHAVAN MENON, ADAM GOLDSTEIN, MARK D. GRISWOLD, MITRI I. HALABI, MOHAMMAD K. ISSA, AMIR LEHAVOT, SHAHAM PARVIN, XIAOYANG ZHENG
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Publication number: 20090144680Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.Type: ApplicationFiled: October 31, 2008Publication date: June 4, 2009Applicant: Cadence Design Systems, Inc.Inventors: Amir LEHAVOT, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer
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Publication number: 20090144683Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.Type: ApplicationFiled: October 31, 2008Publication date: June 4, 2009Applicant: Cadence Design Systems, Inc.Inventors: Amir Lehavot, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer
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Publication number: 20090144681Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.Type: ApplicationFiled: October 31, 2008Publication date: June 4, 2009Applicant: Cadence Design Systems, Inc.Inventors: Amir LEHAVOT, Vinaya Kumar SINGH, Joezac John ZACHARIAH, Jose BARANDIARAN, Axel Siegfried SCHERER
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Patent number: 7505458Abstract: Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.Type: GrantFiled: November 27, 2001Date of Patent: March 17, 2009Assignee: Tellabs San Jose, Inc.Inventors: Raghavan Menon, Adam Goldstein, Mark D Griswold, Mitri I Halabi, Mohammad K Issa, Amir Lehavot, Shaham Parvin, Xiaoyang Zheng
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Publication number: 20030103500Abstract: Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.Type: ApplicationFiled: November 27, 2001Publication date: June 5, 2003Inventors: Raghavan Menon, Adam Goldstein, Mark D. Griswold, Mitri I Halabi, Mohammad K. Issa, Amir Lehavot, Shaham Parvin, Xiaoyang Zheng
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Patent number: 5825217Abstract: A design method using a device with a capacitance inserted in between the output of a MOS circuit and it's corresponding load. This creates a smaller equivalence capacitance to be seen by the MOS circuit. This in turn creates faster switching times and lower power dissipation. Careful design of the circuits which have the capacitor that was added in their input stage is necessary since the high voltage level that these circuits will see is now modified due to the voltage divider created by the added capacitor and the load capacitance. With careful optimization of all parameters involved, circuits could achieve superior switching speed or superior power performance or both compared to other circuits of the same size that do not use this technique.Type: GrantFiled: May 21, 1997Date of Patent: October 20, 1998Assignee: Amir LehavotInventor: Amir Lehavot