Abstract: A hybrid computer that comprises a sequential processor, a single instruction massively parallel (SIMD) processor, and shared memory module that is shared between the sequential processor and the SIMD processor.

Abstract: A hybrid computer that comprises a sequential processor, a single instruction massively parallel (SIMD) processor, and shared memory module that is shared between the sequential processor and the SIMD processor.

Abstract: The present invention provides a buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.

Abstract: An apparatus is disclosed for performing real time video/audio encoding on a single chip. Within the single chip, a video encoder generates encoded video data from uncompressed video data and an audio encoder generates encoded audio data from uncompressed audio data. A mux processor within the single chip generates an output stream of encoded data from the encoded video data and the encoded audio data.

Abstract: An apparatus is disclosed for performing real time video/audio encoding on a single chip. Within the single chip, a video encoder generates encoded video data from uncompressed video data and an audio encoder generates encoded audio data from uncompressed audio data. A mux processor within the single chip generates an output stream of encoded data from the encoded video data and the encoded audio data.

Abstract: The present invention provides a buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.

Abstract: User end communication apparatus for managing broadcast channel input within a user end environment, comprises: a channel probe for obtaining channel context data from a stream at least passing through said user end communication apparatus; a keyword/key concept extractor for extracting channel keywords from the channel context data; and a content selector for selecting a content item or stream for mixing into a channel currently being viewed based on the channel keyword/key concept.

Abstract: Apparatus for automotive entertainment, navigation, communication and control, including a plurality of radio, TV, video and audio inputs, a video and audio output, a plurality of wireless communication channels, and a plurality of receivers, transceivers and processing units.

Abstract: Apparatus for processing audio signal streams including a plurality of audio signal inputs, an audio signal output, and a plurality of audio signal processing units, wherein the audio signal input, the audio signal output, and the plurality of audio signal processing units are connected to and controlled by a Micro Controller Unit (MCU), and wherein the audio signal processing units are configured to process more than one audio signal stream at the same time. Related apparatus and methods are also described.

Abstract: A method for estimating image-to-image motion of a pixel block in a stream of images which includes a current image which includes the pixel block and a reference image, the method including performing a hierarchical search in a search area of the reference image, including producing a decimated reference image and a decimated pixel block, searching for a location in the search area of the decimated reference image which best fits the decimated pixel block, repeating the producing and the searching for more than one level of hierarchy, determining a first candidate location in the reference image which corresponds to the best fitting location, determining a second candidate location in the reference image by a method other than the hierarchical search, performing a search in the reference image for refined locations of the first and the second candidate locations, selecting one final location from the refined candidate locations, and using the final location for estimating the motion.

Abstract: A media stream transcoding set top box including an RF input interface, an RF receiver configured to receive from the RF input interface an RF signal including an original digital media stream, and produce an input digital media stream based, at least in part, on the original digital media stream, the input digital media stream including one or more channels, the channels carrying at least one media stream, a decoder configured to receive the input digital media stream and extract therefrom an uncompressed media stream, a processor configured to process the uncompressed media stream, to produce a processed media stream, an encoder configured to compress the processed media stream, to produce a compressed processed digital media stream, and an output interface configured to output the compressed processed digital media stream in a format suitable for a client device. Related apparatus and methods are also described.

Abstract: An integrated circuit for processing a media stream, including an RF input interface, an RF receiver unit configured for receiving an RF media stream from the RF input interface and extracting the media stream from the RF media stream, an input interface unit configured for receiving the media stream from a content source, a plurality of processing units, a switch, operatively connected to the RF receiver unit, to the input interface unit, and to each of the processing units, the switch configured to allow more than one of the operatively connected units to simultaneously receive the media stream, thereby allowing simultaneous processing of the media stream by the processing units, and an output interface, operatively connected to the switch, configured for outputting the simultaneously processed media stream. Related apparatus and methods are also described.

Abstract: Apparatus for performing multiplexing and de-multiplexing of packetized digital data streams, including receivers for receiving data packets from packetized digital data streams, validating the packets, and transmitting only valid packets, PID filters for filtering packets according to a Packet ID included in the packets, the filters receiving valid packets from the receivers, and associating a store-or-drop value with each valid packet, input FIFO buffers for receiving valid packets from the receivers, receiving the store-or-drop value from the PID filters, and storing data based, at least in part, on the store-or-drop value, an input/output unit for transmitting the stored data from the input FIFO buffers to an external memory and reading data from the external memory, output FIFO buffers for receiving data from the input/output unit and storing the data, and transmitters for reading digital data packets from the output FIFO buffers and transmitting the packets as a packetized digital data stream, thereby d

Abstract: The present invention provides a buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.

Abstract: Video format transformation apparatus including a field/frame assessment module, for associating a field/frame value with a specific pixel. A first value is associated with the specific pixel based on a first function of a group of pixels in proximity to the specific pixel, the group of pixels being in a video frame which includes the specific pixel. A second value is associated with the specific pixel based on a first result and a second result. The first result is of a second function of a second group of pixels, including pixels of an even parity video field within the video frame. The second result is of the second function of a third group of pixels, including pixels of an odd parity video field within the video frame. The field/frame value is associated with the specific pixel based on a third function of the first value and the second value.

Abstract: An integrated circuit for pre-processing, encoding, decoding, transcoding, indexing, blending, post-processing and display of media streams, in accordance with a variety of compression algorithms, DRM schemes and related industry standards and recommendations such as OCAP, ISMA, DLNA, MPAA etc. The integrated circuit comprises an input interface configured for receiving the media streams from content sources, a plurality of processing units, system CPU, and sophisticated switch and memory controller, electronically connected to the input interface and directly connected to each one of the processing units. The integrated circuit further comprises an output interface that is operatively connected to the switch and configured for outputting the simultaneously processed media streams.

Abstract: A home gateway for a home media network. The home gateway comprises a number of input interfaces each configured for receiving encrypted & unencrypted data from a content source, a layout generation unit adapted to generate substantially simultaneously a number of different composite layout streams. Each one of the different composite layout streams is generated according to one or more of the number of input interfaces. The home gateway further comprises a number of output interfaces for providing a number of client stations with the ability to access one or more of the number of different composite layout streams in encrypted & unencrypted manner.

Abstract: A buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.

Abstract: The present invention provides a buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.

Abstract: A buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for proficient division of the encoding task and quicker through put time. A single chip digital signal processing device for real time video/audio compression comprises a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.