Abstract: A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on and turned off, and the chip end of the data line is connected to a positive or to a less positive, grounded, or negative supply voltage line by a pull-up or pull-down resistor. Alternatively, a data transmission system is operated with a timing by which the termination circuits to be turned on for respective operating state are not turned on until the drivers to be activated for the respective operating state have been activated.

Abstract: A method of developing the physical layout of an electronic component in a data bus connected logic analog system includes: providing a data bus connected logic analog system modeled as a software-implemented channel simulation model including: a bit pattern generator for generating a bit pattern; the electronic component, whose physical layout is to be determined by being modeled as a black box characterized by model parameters; and a bit pattern analyzer for analyzing a bit error rate of the bit pattern; sending an input bit pattern through the black box to produce an output bit pattern and comparing the output bit pattern with the input bit pattern to determine a bit error rate; and varying the model parameters and repeating the process until the determined bit error rate is below a pre-determined value to determine at least one critical model parameter boundary.

Abstract: A method of developing the physical layout of an electronic component in a data bus connected logic analog system includes: providing a data bus connected logic analog system modeled as a software-implemented channel simulation model including: a bit pattern generator for generating a bit pattern; the electronic component, whose physical layout is to be determined by being modeled as a black box characterized by model parameters; and a bit pattern analyzer for analyzing a bit error rate of the bit pattern; sending an input bit pattern through the black box to produce an output bit pattern and comparing the output bit pattern with the input bit pattern to determine a bit error rate; and varying the model parameters and repeating the process until the determined bit error rate is below a pre-determined value to determine at least one critical model parameter boundary.

Abstract: A multi-chip package and method is disclosed. In one embodiment, the multi-chip package includes at least four of spaced semiconductor integrated circuit chips mounted on a printed circuit board, consisting of the first pair of the semiconductor integrated circuit chips and the second pair of the semiconductor integrated circuit chips. The chips of the first pair of the semiconductor integrated circuit chips are arranged substantially parallel and the chips of the semiconductor integrated circuit chips of the second pair are arranged substantially stacked over the chips of the first pair of the semiconductor integrated circuit chips.

Abstract: A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on and turned off, and the chip end of the data line is connected to a positive or to a less positive, grounded, or negative supply voltage line by a pull-up or pull-down resistor. Alternatively, a data transmission system is operated with a timing by which the termination circuits to be turned on for respective operating state are not turned on until the drivers to be activated for the respective operating state have been activated.