Abstract: A method for determining a value of a manufacturing parameter of a resistive memory cell, the resistive memory cell including a stack of layers, includes providing reference memory cells corresponding to technological alternatives of the stack of layers; measuring for each reference memory cell an initial resistance value; determining for each reference memory cell a programming parameter value selected from among the resistance in a high resistance state and the programming window; establishing a relationship between the programming parameter and the initial resistance from the initial resistance values and the programming parameter values; and determining the manufacturing parameter value for which the programming parameter is greater than or equal to a target value, from the relationship between the programming parameter and the initial resistance and from a dependency relationship between the initial resistance and the manufacturing parameter.

Abstract: A method for resetting an array of RAM cells by applying a sequence of N reset operations, the method including at a first reset operation, defining a first reset technique and performing the first reset operation; at a j-th reset operation of a N?1 subsequent reset operations, j being an integer between 2 and N, if a correction yield of the reset technique used at the (j?1)-th reset operation fulfils a predefined condition, applying the reset technique used at the (j?1)-th reset operation to perform the j-th reset operation, if the correction yield does not fulfil the predefined condition, defining a new reset technique and applying the new reset technique to perform the j-th reset operation, the correction yield being a cumulative correction yield or a relative correction yield, the correction yield for the N reset operations being measured prior to the first reset operation.

Abstract: A method for programming at least one resistive memory cell of an array of resistive memory cells, includes a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle including a set procedure and a reset procedure, each set procedure including the application of a set technique chosen among a plurality of set techniques, the method including acquiring a bit error ratio value corresponding to each programming cycle for each set technique; and at each programming cycle, applying the set technique having the lowest bit error ratio value corresponding to the programming cycle.

Abstract: A memory includes a matrix of resistive memory cells and an interfacing device to interface the matrix, the interfacing device including at least a conversion capacitor, an electric source, a first switch and a second switch, the interfacing device being configured to: a) connect the conversion capacitor to the source by the second switch to charge the conversion capacitor, then, b) disconnect the conversion capacitor from the source and connect the conversion capacitor to the matrix to achieve a conversion between, on the one hand, a resistive state of one of the memory cells of the matrix, and, on the other hand, a state of charge of the conversion capacitor.

Abstract: A method for resetting an array of Resistive Memory cells by applying a sequence of N reset operations, each reset operation including the application of a reset technique, the method including, at the first reset operation, performing the first reset operation by applying the reset technique having the highest relative correction yield; at the j-th reset operation of the N?1 subsequent reset operations, j being an integer number between 2 and N, defining a reset technique to be used at the j-th reset operation and performing the j-th reset operation.

Abstract: A memory includes at least one resistive memory cell and a write device. The memory cell includes a memory element having at least a highly resistive state and a lowly resistive state, and a selector arranged in series with the memory element, the selector being electrically conductive when a voltage greater than a given threshold voltage is applied to the selector. The write device includes at least one write capacitor and one charging device, and is configured to charge the write capacitor and then to connect it to the memory cell to program that cell.

Abstract: A method for resetting an array of Resistive Memory cells by applying a sequence of N reset operations, each reset operation including the application of a reset technique, the method including, at the first reset operation, performing the first reset operation by applying the reset technique having the highest relative correction yield; at the j-th reset operation of the N?1 subsequent reset operations, j being an integer number between 2 and N, defining a reset technique to be used at the j-th reset operation and performing the j-th reset operation.

Abstract: A method for resetting an array of RAM cells by applying a sequence of N reset operations, the method including at a first reset operation, defining a first reset technique and performing the first reset operation; at a j-th reset operation of a N-1 subsequent reset operations, j being an integer between 2 and N, if a correction yield of the reset technique used at the (j-1)-th reset operation fulfils a predefined condition, applying the reset technique used at the (j-1)-th reset operation to perform the j-th reset operation, if the correction yield does not fulfil the predefined condition, defining a new reset technique and applying the new reset technique to perform the j-th reset operation, the correction yield being a cumulative correction yield or a relative correction yield, the correction yield for the N reset operations being measured prior to the first reset operation.

Abstract: An OxRAM resistive memory cell includes a lower electrode, an upper electrode, and an active layer which extends between the lower electrode and the upper electrode. The active layer includes a layer of a first electrically insulating oxide, wherein an electrically conductive filament can be formed, then subsequently broken and reformed several times successively. The upper electrode includes a reservoir layer, capable of receiving oxygen, which includes an upper part made of a metal and a lower part made of a second oxide, the second oxide being an oxide of the metal and including a proportion of oxygen such that the second oxide is electrically conductive.

Abstract: A method for programming at least one resistive memory cell of an array of resistive memory cells, includes a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle including a set procedure and a reset procedure, each set procedure including the application of a set technique chosen among a plurality of set techniques, the method including acquiring a bit error ratio value corresponding to each programming cycle for each set technique; and at each programming cycle, applying the set technique having the lowest bit error ratio value corresponding to the programming cycle.

Abstract: A method for manufacturing an OxRAM type resistive memory cell including a silicon oxide layer, the method including determining manufacturing parameter values enabling the resistive memory cell to have an initial resistance between 107? and 3·109?; and forming on a substrate a stack successively including a first electrode, the silicon oxide layer and a second electrode, by applying the manufacturing parameter values.

Abstract: A method for determining a value of a manufacturing parameter of a resistive memory cell, the resistive memory cell including a stack of layers, includes providing reference memory cells corresponding to technological alternatives of the stack of layers; measuring for each reference memory cell an initial resistance value; determining for each reference memory c ell a programming parameter value selected from among the resistance in a high resistance state and the programming window; establishing a relationship between the programming parameter and the initial resistance from the initial resistance values and the programming parameter values; and determining the manufacturing parameter value for which the programming parameter is greater than or equal to a target value, from the relationship between the programming parameter and the initial resistance and from a dependency relationship between the initial resistance and the manufacturing parameter.

Abstract: A memory includes a matrix of resistive memory cells and an interfacing device to interface the matrix, the interfacing device including at least a conversion capacitor, an electric source, a first switch and a second switch, the interfacing device being configured to: a) connect the conversion capacitor to the source by the second switch to charge the conversion capacitor, then, b) disconnect the conversion capacitor from the source and connect the conversion capacitor to the matrix to achieve a conversion between, on the one hand, a resistive state of one of the memory cells of the matrix, and, on the other hand, a state of charge of the conversion capacitor.