Abstract: A message based processor system (1) with a plurality of message based processor system cores (100) is proposed. Cores therein comprise a processor element controller that is configured to receive a message with an indication of a subset processor elements in the core to which it is directed as well as an indication of a target pattern, and to update the state value of the processor elements (Ei) in the subset in accordance with a specification of the target pattern. The processor element controller (PEC) is configurable in an address computation mode selected from a cyclic set of address computation modes, and configured to maintain its computation mode or assume a next address computation mode selected from the cyclic set dependent on a control value of a currently applied pattern element. Therewith a target pattern can efficiently specified.

Abstract: A neuro-synaptic processing circuitry for performing neuro-synaptic operations based on synaptic weights and neuron states and comprises i) a data memory for storing the synaptic weights and neuron states; the data memory having a first memory port for loading and storing data from and to the data memory; ii) a plurality of neuron processing elements, NPEs, configurable to execute NPE instructions in parallel according to a single instruction, multiple data, SIMD, instruction set; wherein the NPEs have access to respective portions of the memory port; the SIMD instruction set comprising instructions for loading and storing the synaptic weights and neuron states from and to the memory port, and for performing the neuro-synaptic operations; iii) a general-purpose central processing unit, GP-CPU, configured to execute program code; iv) a loop buffer having a register-based memory; an address calculation unit; and a program counter.

Abstract: A message based processor system (1) with a plurality of message based processor system cores (100) is proposed. Cores therein comprise a processor element controller that is configured to receive a message with an indication of a subset processor elements in the core to which it is directed as well as an indication of a target pattern, and to update the state value of the processor elements (Ei) in the subset in accordance with a specification of the target pattern. The processor element controller (PEC) is configurable in an address computation mode selected from a cyclic set of address computation modes, and configured to maintain its computation mode or assume a next address computation mode selected from the cyclic set dependent on a control value of a currently applied pattern element. Therewith a target pattern can efficiently specified.

Abstract: A neural network processor is provided comprising a plurality of mutually succeeding neural network processor layers is provided. A neural network processor layer therein comprising a plurality of neural network processor elements (1) having a respective state register (2) for storing a state value (X) indicative for their state, as well as an additional state register (4) for storing a value (Q) of a state value change indicator that is indicative for a direction of a previous state change exceeding a threshold value. Neural network processor elements in a neural network processor layer are configured to selectively transmit differential event messages indicative for a change of their state, dependent both on the change of their state value and on the value of their state value change indicator.

Abstract: A neuromorphic processing system (1) is disclosed comprising a plurality of neuromorphic processing clusters (100) coupled to a message exchange network (20) for exchange of event messages. A neuromorphic cluster therein comprises a message receiving facility (110) to receive event messages from the message exchange network, a message transmitting facility (120) to transmit event messages via the message exchange network and a neuromorphic processor (130) having a set of state memory entries (10 j) for storing a value representative of a neuromorphic state associated with a neuromorphic element and a computation facility (134) to update the neuromorphic state associated with neuromorphic elements that are indicated as the destination of the event message. The message receiving facility (110) and/or the message transmitting facility (120) are enhanced to enable message distribution according to a pattern.

Abstract: A neuromorphic processor and a neuromorphic processing method are provided comprising plurality of neuromorphic elements (i=1, i=n), a message exchange facility (20), and a computation unit (30). The plurality of neuromorphic elements has a respective state memory entry (10_j) for storing their state. The message exchange facility (20) enables neuromorphic elements to transmit neural event messages, and to receive transmitted neural event messages, a neural event message including an indication (NA) of one or more neuromorphic elements selected as the destination, a message type (MT) and one or more message parameters (MP1, . . . , MPm). The computation unit (30) is to update the state dependent on received neural event messages. The message type is one of at least an accumulation message (A) and a leakage message (L).

Abstract: A neuron circuit performing synapse learning on weight values includes a first sub-circuit, a second sub-circuit, and a third sub-circuit. The first sub-circuit is configured to receive an input signal from a pre-synaptic neuron circuit and determine whether the received input signal is an active signal having an active synapse value. The second sub-circuit is configured to compare a first cumulative reception counter of active input signals with a learning threshold value based on results of the determination. The third sub-circuit is configured to perform a potentiating learning process based on a first probability value to set a synaptic weight value of at least one previously received input signal to an active value, upon the first cumulative reception counter reaching the learning threshold value, and perform a depressing learning process based on a second probability value to set each of the synaptic weight values to an inactive value.

Abstract: A neuron circuit performing synapse learning on weight values includes a first sub-circuit, a second sub-circuit, and a third sub-circuit. The first sub-circuit is configured to receive an input signal from a pre-synaptic neuron circuit and determine whether the received input signal is an active signal having an active synapse value. The second sub-circuit is configured to compare a first cumulative reception counter of active input signals with a learning threshold value based on results of the determination. The third sub-circuit is configured to perform a potentiating learning process based on a first probability value to set a synaptic weight value of at least one previously received input signal to an active value, upon the first cumulative reception counter reaching the learning threshold value, and perform a depressing learning process based on a second probability value to set each of the synaptic weight values to an inactive value.