Patents by Inventor Amir Rochman
Amir Rochman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935603Abstract: A non-volatile memory has an array of non-volatile memory cells, first reference word lines and second reference word lines, and sense amplifiers. The sense amplifiers read system data, that has been written to supplemental non-volatile memory cells of the first reference word lines, using comparison of the supplemental non-volatile memory cells of the first reference word lines to supplemental non-volatile memory cells of the second reference word lines. Status of erasure of the non-volatile memory cells of the array is determined based on reading the system data.Type: GrantFiled: January 11, 2022Date of Patent: March 19, 2024Assignee: Infineon Technologies LLCInventors: Amichai Givant, Idan Koren, Shivananda Shetty, Pawan Singh, Yoram Betser, Kobi Danon, Amir Rochman
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Publication number: 20230244409Abstract: Systems, methods, and devices implement counters with fault tolerance and power loss protection. Systems include a non-volatile memory device that includes a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing an initiation and a completion of each erase operation performed on the first counter. Systems also include control circuitry configured to generate a count value based on a current counter value of the first counter, a current counter value of the second counter, and at least one physical parameter of the first counter.Type: ApplicationFiled: January 30, 2023Publication date: August 3, 2023Applicant: Infineon Technologies LLCInventors: Yoav YOGEV, Amichai GIVANT, Amir ROCHMAN, Shivananda SHETTY, Pawan SINGH, Yair SOFER
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Publication number: 20230137469Abstract: A non-volatile memory has an array of non-volatile memory cells, first reference word lines and second reference word lines, and sense amplifiers. The sense amplifiers read system data, that has been written to supplemental non-volatile memory cells of the first reference word lines, using comparison of the supplemental non-volatile memory cells of the first reference word lines to supplemental non-volatile memory cells of the second reference word lines. Status of erasure of the non-volatile memory cells of the array is determined based on reading the system data.Type: ApplicationFiled: January 11, 2022Publication date: May 4, 2023Applicant: Infineon Technologies LLCInventors: Amichai Givant, Idan Koren, Shivananda Shetty, Pawan Singh, Yoram Betser, Kobi Danon, Amir Rochman
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Patent number: 11567691Abstract: Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.Type: GrantFiled: June 19, 2020Date of Patent: January 31, 2023Assignee: INFINEON TECHNOLOGIES LLCInventors: Yoav Yogev, Amichai Givant, Yair Sofer, Amir Rochman, Shivananda Shetty, Pawan Singh
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Patent number: 11537511Abstract: Systems, methods, and devices dynamically configure non-volatile memories. Devices include non-volatile memories comprising a plurality of memory regions, each of the plurality of memory regions having a configurable bit density. Devices also include control circuitry configured to retrieve user partition configuration data identifying a plurality of bit densities for the plurality of memory regions, convert a received user address to a plurality of physical addresses based, at least in part, on the plurality of bit densities, compare the user address with the user partition configuration data, and select one of the plurality of physical addresses based, at least in part, on the comparison.Type: GrantFiled: December 17, 2020Date of Patent: December 27, 2022Assignee: INFINEON TECHNOLOGIES LLCInventors: Amir Rochman, Ori Tirosh, Yi He, Amichai Givant
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Patent number: 11449441Abstract: A memory device that includes a first port and a second port. The first port includes a first clock input, at least one first command address input, and at least one data input or output configured to transfer data in relation to the memory device. The second port includes a second clock input and at least one command, address, and data input/output (I/O) configured to receive command and address information from, and to transfer data in relation to the memory device. The memory device also includes a plurality of memory banks, in which two different memory banks may be accessed respectively by the first and the second ports concurrently. Other embodiments of the memory device and related methods and systems are also disclosed.Type: GrantFiled: May 21, 2021Date of Patent: September 20, 2022Assignee: Cypress Semiconductor CorporationInventors: Yoram Betser, Cliff Zitlaw, Stephan Rosner, Kobi Danon, Amir Rochman
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Publication number: 20220043745Abstract: Systems, methods, and devices dynamically configure non-volatile memories. Devices include non-volatile memories comprising a plurality of memory regions, each of the plurality of memory regions having a configurable bit density. Devices also include control circuitry configured to retrieve user partition configuration data identifying a plurality of bit densities for the plurality of memory regions, convert a received user address to a plurality of physical addresses based, at least in part, on the plurality of bit densities, compare the user address with the user partition configuration data, and select one of the plurality of physical addresses based, at least in part, on the comparison.Type: ApplicationFiled: December 17, 2020Publication date: February 10, 2022Applicant: Infineon Technologies LLCInventors: Amir Rochman, Ori Tirosh, Yi He, Amichai Givant
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Publication number: 20210349839Abstract: A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.Type: ApplicationFiled: May 21, 2021Publication date: November 11, 2021Applicant: Cypress Semiconductor CorporationInventors: Yoram Betser, Cliff Zitlaw, Stephan Rosner, Kobi Danon, Amir Rochman
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Publication number: 20210223983Abstract: Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.Type: ApplicationFiled: June 19, 2020Publication date: July 22, 2021Applicant: Infineon Technologies LLCInventors: Yoav Yogev, Amichai Givant, Yair Sofer, Amir Rochman, Shivananda Shetty, Pawan Singh
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Patent number: 11030128Abstract: A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.Type: GrantFiled: December 18, 2019Date of Patent: June 8, 2021Assignee: Cypress Semiconductor CorporationInventors: Yoram Betser, Cliff Zitlaw, Stephan Rosner, Kobi Danon, Amir Rochman
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Publication number: 20210042245Abstract: A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.Type: ApplicationFiled: December 18, 2019Publication date: February 11, 2021Applicant: Cypress Semiconductor CorporationInventors: Yoram Betser, Cliff Zitlaw, Stephan Rosner, Kobi Danon, Amir Rochman
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Patent number: 10679712Abstract: A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.Type: GrantFiled: December 4, 2018Date of Patent: June 9, 2020Assignee: Cypress Semiconductor CorporationInventors: James Pak, Shivananda Shetty, Yoram Betser, Amichai Givant, Jonas Neo, Pawan Singh, Stefano Amato, Cindy Sun, Amir Rochman
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Publication number: 20190198125Abstract: A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.Type: ApplicationFiled: December 4, 2018Publication date: June 27, 2019Applicant: Cypress Semiconductor CorporationInventors: James Pak, Shivananda Shetty, Yoram Betser, Amichai Givant, Jonas Neo, Pawan Singh, Stefano Amato, Cindy Sun, Amir Rochman
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Patent number: 9537511Abstract: Disclosed are methods for reading a set of bits from a NVM array (such as a SPI or parallel NOR NVM or otherwise) including: retrieving each of the set of bits from the NVM array substantially in parallel, applying substantially in parallel to each of the retrieved bits a segmented search, each search indexed using an order number of the respective bit being checked, and correcting a bit whose search indicates an error.Type: GrantFiled: November 6, 2013Date of Patent: January 3, 2017Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Amir Rochman, Kobi Danon, Avri Harush
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Publication number: 20150128011Abstract: Disclosed are methods for reading a set of bits from a NVM array (such as a SPI or parallel NOR NVM or otherwise) including: retrieving each of the set of bits from the NVM array substantially in parallel, applying substantially in parallel to each of the retrieved bits a segmented search, each search indexed using an order number of the respective bit being checked, and correcting a bit whose search indicates an error.Type: ApplicationFiled: November 6, 2013Publication date: May 7, 2015Applicant: Spansion LLCInventors: Amir Rochman, Kobi Danon, Avri Harush