Abstract: A memory allocator in a computer system comprising a plurality of CPU cores (5101-5104) and a first (530) and a second (5120) memory unit having different data access times and wherein each one of the first and the second memory units is divided into memory portions wherein each memory portion (SLICE 0-3) in the second memory unit is associated with at least one memory portion (A-G) in the first memory unit, and wherein each memory portion in the second memory unit is associated with a CPU core. If at least a predetermined number of memory portions in the first memory unit being part of the available requested memory is associated with the memory portion in the second memory unit that is associated with the CPU core on which the requesting application is running, the requested available memory is allocated to the requesting application.

Abstract: A method of buffering data packets at a network device includes receiving a set of data packets from an ingress port of the network device, identifying primary information and secondary information about each data packet in the set of data packets, determining a virtual queue for each data packets in the set of data packets based on the primary information, the virtual queue having a set of physical queues, determining a physical queue from the set of physical queues for each of the data packets in the set of data packets based on the secondary information, and storing the set of data packets in physical queues of the virtual queue.

Abstract: A method of cache pooling is presented where the method includes determining whether a cache of a primary processor assigned to execute an application has insufficient storage space to allot for the application, select at least one alternative processor from a list of alternative processors based on a cache availability or metric for each processor in the list of alternative processors, configuring the primary processor and the selected at least one alternative processor for mutual cache visibility, and configure routing of traffic to the application to be divided between the primary processor cache and the selected at least one alternative processor cache.

Abstract: There is provided mechanisms for initiating writing data of a pending memory write on a host computer. A method comprises monitoring pending memory writes for a non-volatile memory write indicator (NVMWI). The NVMWI is either set or not set. The method comprises initiating writing of the data of the pending memory write. Writing of the data is initiated to both a non-volatile memory (NVM) and a volatile memory (VM) when the NVMWI for the pending memory write is set. Writing of the data otherwise is initiated only to the VM.

Abstract: A method and device for controlling memory handling in a processing system comprising a cache shared between a plurality of processing units, wherein the cache comprises a plurality of cache portions. The method comprises obtaining first information pertaining to an allocation of a first memory portion of a memory to a first application, an allocation of a first processing unit of the plurality of processing units to the first application, and an association between a first cache portion of the plurality of cache portions and the first processing unit. The method further comprises reconfiguring a mapping configuration based on the obtained first information, and controlling a providing of first data associated with the first application to the first cache portion from the first memory portion using the reconfigured mapping configuration.

Abstract: Embodiments herein relates e.g., to a method performed by a first entity, for handling memory operations of an application in a computer environment, is provided. The first entity obtains position data associated with data of the application being fragmented into a number of positions in a physical memory. The position data indicates one or more positions of the number of positions in the physical memory. The first entity then provides, to a second entity, one or more indications of the one or more positions indicated by the position data for prefetching data from the second entity, using the one or more indications.

Abstract: A method performed by a coordinating entity in a disaggregated data center architecture wherein computing resources are separated in discrete resource pools and associated together to represent a functional server. The coordinating entity obtains a setup of processor cores that are coupled logically as the functional server, and determines an index indicating an identity of a cache coherency domain based on the obtained setup of processor cores. The coordinating entity further configures one or more communicating entities associated with the obtained setup of processor cores, to use the determined index when handling updated cache related data.

Abstract: There is provided mechanisms for snapshotting data of a host application. A method is performed by a field-programmable gate array (FPGA). The method comprises snooping a cache coherent interconnect of a host computer on which the host application is running. The cache coherent interconnect is snooped for dirty cache lines, each dirty cache line having an address. The method comprises writing, only when the address of any of the dirty cache lines has a match in a snapshot address table, data of that dirty cache line to a non-volatile memory.

Abstract: Methods and systems for selective access to a processing unit are described. An electronic device that is coupled with the processing unit for processing packets is described. The electronic device is operative to receive a packet; determine based on one or more attributes of the packet that the packet is to be split; and responsive to determining that the packet is to be split, splitting the packet into a first portion and a second portion, where the first portion is to be processed by the processing unit and the second portion is to be stored without being processed by the processing unit; sending the first portion of the packet toward the processing unit for processing; and storing the second portion of the packet.

Abstract: Methods and systems for selective direct access to a processing unit of a network device are described. A network interface of the network device receives packets of a flow. The network interface determines based on attributes of the packets that the packets are to be directly sent to the processing unit. In response to determining that the packets are to be directly sent to the processing unit, they are directly sent to the processing unit for processing.

Abstract: There is provided mechanisms for initiating writing data of a pending memory write on a host computer. A method comprises monitoring pending memory writes for a non-volatile memory write indicator (NVMWI). The NVMWI is either set or not set. The method comprises initiating writing of the data of the pending memory write. Writing of the data is initiated to both a non-volatile memory (NVM) and a volatile memory (VM) when the NVMWI for the pending memory write is set. Writing of the data otherwise is initiated only to the VM.

Abstract: A method performed by a coordinating entity in a disaggregated data center architecture wherein computing resources are separated in discrete resource pools and associated together to represent a functional server. The coordinating entity obtains a setup of processor cores that are coupled logically as the functional server, and determines an index indicating an identity of a cache coherency domain based on the obtained setup of processor cores. The coordinating entity further configures one or more communicating entities associated with the obtained setup of processor cores, to use the determined index when handling updated cache related data.

Abstract: A system and method to distribute traffic flows among a plurality of applications in a data center system. An apparatus is operable with a plurality of applications connected through a programmable switch and is configured to select traffic flows to ones of the plurality of applications. The apparatus is also configured to monitor and collect statistics for the traffic flows to determine rule level statistics, and move at least one traffic flow of the traffic flows from a network interface to a different network interface based on the rule level statistics.

Abstract: A method performed by a coordinating entity in a disaggregated data center architecture wherein computing resources are separated in discrete resource pools and associated together to represent a functional server. The coordinating entity obtains a setup of processor cores that are coupled logically as the functional server, and determines an index indicating an identity of a cache coherency domain based on the obtained setup of processor cores. The coordinating entity further configures one or more communicating entities associated with the obtained setup of processor cores, to use the determined index when handling updated cache related data.

Abstract: It is disclosed a resource sharing manager, RSM, operative to provide efficient utilization of central processing units, CPUs, within virtual servers, each virtual server having an operating system, OS. The RSM dynamically obtains (902) information about ownership and sharable status of said CPUs, and dynamically determines (904) which CPUs are sharable to which virtual servers. The RSM obtains (906) information about that one or more sharable CPUs are available; and obtains (908) information about that one or more virtual servers require more processing resources. The RSM also assigns (910) a first CPU of said sharable CPUs when available, to a first virtual server of said virtual servers. Information about ownership and sharable status of the first CPU, is hence provided to the OS of the first virtual server. Overhead is reduced by circumventing a hypervisor when sharing CPUs in virtual servers. An increase in efficiency of task execution is provided.

Abstract: A method in a multi-core processing system which comprises a processor comprising at least a first and a second processing unit, a cache, common to the first and the second processing unit, comprising a first cache portion associated with the first processing unit and a second cache portion associated with the second processing unit, a memory, comprising a first memory portion associated with the first cache portion and a second memory portion associated with the second cache portion. The method comprises detecting that a data access criteria of the second memory portion is fulfilled, establishing that first data stored in the second memory portion is related to a first application running on the first processing unit, allocating at least a part of the first memory portion to the first application based on cache information, and migrating the first data to the part of first memory portion.

Abstract: A memory allocation manager and a method performed thereby for managing memory allocation, within a data centre, to an application are provided. The data centre comprises at least a Central Processing Unit, CPU, pool and at least one memory pool. The method comprises receiving (210) information associated with a plurality of instances associated with an application to be initiated, wherein individual instances are associated with individual memory requirements, the information further comprising information about an internal relationship between the instances; and determining (230) for a plurality of instances, a minimum number of memory blocks and associated sizes required based on the received information, by identifying parts of memory blocks and associated sizes that may be shared by two or more instances based on their individual memory requirements and/or the internal relationship between the instances.

Abstract: There is provided mechanisms for snapshotting data of a host application. A method is performed by a field-programmable gate array (FPGA). The method comprises snooping a cache coherent interconnect of a host computer on which the host application is running. The cache coherent interconnect is snooped for dirty cache lines, each dirty cache line having an address. The method comprises writing, only when the address of any of the dirty cache lines has a match in a snapshot address table, data of that dirty cache line to a non-volatile memory.

Abstract: A performance manager (400, 500) and a method (200) performed thereby are provided, for managing the performance of a logical server of a data center. The data center comprises at least one memory pool in which a memory block has been allocated to the logical server. The method (200) comprises determining (230) performance characteristics associated with a first portion of the memory block, comprised in a first memory unit of the at least one memory pool; and identifying (240) a second portion of the memory block, comprised in a second memory unit of the at least one memory pool, to which data of the first portion of the memory block may be migrated to apply performance characteristics associated with the second portion. The method (200) further comprises initiating migration (250) of the data to the second portion of the memory block.

Abstract: A method performed by a coordinating entity in a disaggregated data center architecture wherein computing resources are separated in discrete resource pools and associated together to represent a functional server. The coordinating entity obtains a setup of processor cores that are coupled logically as the functional server, and determines an index indicating an identity of a cache coherency domain based on the obtained setup of processor cores. The coordinating entity further configures one or more communicating entities associated with the obtained setup of processor cores, to use the determined index when handling updated cache related data.