Patents by Inventor Amir Rosen

Amir Rosen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250181510
    Abstract: In one embodiment, a method includes receiving data of a set of configurations of preprocessor engines, receiving measurements of performance of a device executing benchmark applications while changing a configuration of preprocessor engines selected from the set of configurations of preprocessor engines, defining an order of at least some of the configurations based on the measurements, and providing a pruned set of configurations based on the defined order of the at least some configurations.
    Type: Application
    Filed: December 3, 2023
    Publication date: June 5, 2025
    Inventors: Amir Rosen, Shie Mannor, Sagi Lahav, Gil Levy, Ariel Szapiro
  • Publication number: 20250181411
    Abstract: In one embodiment, a system includes a processor to control a resource according to policies selected by a multi-armed bandit machine learning agent in exploration phases and in exploitation phases, and execute the multi-armed bandit machine learning agent to select from the policies to control the resource in the exploration phases according to probabilities to explore corresponding one of the policies, wherein the probabilities include different probabilities, perform measurements on the system during execution of the multi-armed bandit machine learning agent, and execute the multi-armed bandit machine learning agent to select from the policies to maximize potential rewards from controlling the resource in exploitation phases based on the performed measurements, and a memory to store data used by the processor.
    Type: Application
    Filed: December 3, 2023
    Publication date: June 5, 2025
    Inventors: Amir Rosen, Shie Mannor, Gil Levy, Arye Albahari, Ariel Szapiro
  • Publication number: 20250181474
    Abstract: In one embodiment, a method includes finding an impact on performance of a device from changing settings of preprocessor engines applied to benchmark applications being executed by the device, defining groups of the preprocessor engines responsively to the impact on the performance of the device from changing the settings of the preprocessor engines, and providing different preprocessor engine configurations based on the settings to be applied to the preprocessor engines such that for each one of the defined groups a respective setting is to be applied equally to the preprocessor engines of the one group, thereby reducing a number of the preprocessor engine configurations available for selection by a machine learning agent.
    Type: Application
    Filed: December 3, 2023
    Publication date: June 5, 2025
    Inventors: Amir Rosen, Shie Mannor, Sagi Lahav, Gil Levy, Ariel Szapiro
  • Publication number: 20250181968
    Abstract: In one embodiment, a system includes a processor to receive machine learning training data including label scores based on measurements of device performance during execution of benchmark applications for different prefetcher engine configurations, and corresponding device hardware states, and train configuration specific machine learning regression models based on the received machine learning training data to provide corresponding configuration specific device performance predictions based on given device hardware states, and a memory to store data used by the processor.
    Type: Application
    Filed: December 3, 2023
    Publication date: June 5, 2025
    Inventors: Ariel Szapiro, Gil Levy, Shie Mannor, Gaby Diengott, Elad Alon, Sagi Lahav, Amir Rosen
  • Publication number: 20250181509
    Abstract: In one embodiment, a system includes prefetcher engines to predict next memory access addresses of a memory from which to load data to a cache during execution of a software application, and load the data from the predicted next memory access addresses to the cache during execution of the software application, and a processor to control the prefetcher engines according to configurations of the prefetcher engines selected by a machine learning agent in exploration phases and in exploitation phases during execution of the software application, and execute the machine learning agent to select from a pruned set of configurations to control the prefetcher engines in the exploration phases, perform measurements on the system during execution of the machine learning agent, and execute the machine learning agent to select from the configurations to maximize potential rewards from controlling the prefetcher engines in the exploitation phases based on the performed measurements.
    Type: Application
    Filed: December 3, 2023
    Publication date: June 5, 2025
    Inventors: Shie Mannor, Ariel Szapiro, Gil Levy, Arye Albahari, Gaby Diengott, Elad Alon, Sagi Lahav, Amir Rosen
  • Patent number: 11182205
    Abstract: An apparatus includes multiple processors, a classifier and queue management logic. The classifier is configured to classify tasks, which are received for execution by the processors, into multiple processor queues, each processor queue associated with a single processor or thread, and configured to temporarily store task entries that represent the tasks, and to send the tasks for execution by the associated processors. The queue management logic is configured to set, based on queue-lengths of the queues, an affinity strictness measure that quantifies a strictness with which the tasks of a same classified queue are to be processed by a same processor, and to assign the task entries to the queues while complying with the affinity strictness measure.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: November 23, 2021
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Amir Rosen, Tsofia Eshel
  • Publication number: 20200210230
    Abstract: An apparatus includes multiple processors, a classifier and queue management logic. The classifier is configured to classify tasks, which are received for execution by the processors, into multiple processor queues, each processor queue associated with a single processor or thread, and configured to temporarily store task entries that represent the tasks, and to send the tasks for execution by the associated processors. The queue management logic is configured to set, based on queue-lengths of the queues, an affinity strictness measure that quantifies a strictness with which the tasks of a same classified queue are to be processed by a same processor, and to assign the task entries to the queues while complying with the affinity strictness measure.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Inventors: Amir Rosen, Tsofia Eshel
  • Patent number: 10645033
    Abstract: In a packet network of ingress nodes and egress nodes connected by a fabric transmit queues are associated with a hash table that stores packet descriptors. When new packets are received in the ingress nodes, credits are obtained from the egress nodes that reflect capacities of the transmit queues to accommodate the new packets. The credits are consumed by transmitting at least a portion of the new packets from the ingress nodes to the egress nodes via the fabric and storing descriptors of the new packets in a hash table. In order to transmit the packets in order by sequence number, when a desired packet sequence number is found by a hash lookup, the new packet having that sequence number is forwarded through the egress nodes.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: May 5, 2020
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Amir Rosen, Gil Levy
  • Publication number: 20180278550
    Abstract: In a packet network of ingress nodes and egress nodes connected by a fabric transmit queues are associated with a hash table that stores packet descriptors. When new packets are received in the ingress nodes, credits are obtained from the egress nodes that reflect capacities of the transmit queues to accommodate the new packets. The credits are consumed by transmitting at least a portion of the new packets from the ingress nodes to the egress nodes via the fabric and storing descriptors of the new packets in a hash table. In order to transmit the packets in order by sequence number, when a desired packet sequence number is found by a hash lookup, the new packet having that sequence number is forwarded through the egress nodes.
    Type: Application
    Filed: March 27, 2017
    Publication date: September 27, 2018
    Inventors: Amir Rosen, Gil Levy