Patents by Inventor Amir Rozen
Amir Rozen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11983428Abstract: Systems and methods for data migration via a peer communication channel between data storage devices are disclosed. The data storage devices include a host interface configured to connect to at least one host system and a peer interface to connect to the peer communication channel, where the host interface and the peer interface and separate physical interfaces. A source data storage device establishes peer communication with a destination data storage device over the peer communication channel, determines a set of host data, and sends the set of host data to the destination data storage device, while continuing to receive and process host storage operations through the host interface.Type: GrantFiled: June 7, 2022Date of Patent: May 14, 2024Assignee: Western Digital Technologies, Inc.Inventors: Shay Benisty, Amir Rozen, Amir Segev
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Patent number: 11853218Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, wherein the command comprises a plurality of logical block addresses (LBAs), determine that one or more LBAs of the plurality of LBAs are not aligned to a transfer layer packet (TLP) boundary, determine whether the one or more LBAs that are not aligned to a TLP boundary has a head that is unaligned that matches a previously stored tail that is unaligned, and merge and transfer the head that is unaligned with a previously stored tail that is unaligned when the head that is unaligned matches the previously stored tail that is unaligned.Type: GrantFiled: May 18, 2022Date of Patent: December 26, 2023Assignee: Western Digital Technologies, Inc.Inventors: Amir Segev, Amir Rozen, Shay Benisty
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Publication number: 20230393772Abstract: Systems and methods for data migration via a peer communication channel between data storage devices are disclosed. The data storage devices include a host interface configured to connect to at least one host system and a peer interface to connect to the peer communication channel, where the host interface and the peer interface and separate physical interfaces. A source data storage device establishes peer communication with a destination data storage device over the peer communication channel, determines a set of host data, and sends the set of host data to the destination data storage device, while continuing to receive and process host storage operations through the host interface.Type: ApplicationFiled: June 7, 2022Publication date: December 7, 2023Inventors: Shay Benisty, Amir Rozen, Amir Segev
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Patent number: 11537524Abstract: The present disclosure generally relates to effective transport layer packet (TLP) utilization. When the controller of the data storage device generates a request for transferring data to or from the storage device, the request is stored in a merging buffer. The merging buffer may include previously generated requests, where the previously generated requests and the new requests are merged. A timeout counter is initialized for the requests stored in the merging buffer. The timeout counter has a configurable threshold value that corresponds to a weight value, adjusted for latency or bandwidth considerations. When the merged request is greater than the maximum TLP size, the merged request is partitioned, where at least one partition is in the size of the maximum TLP size. The request is sent from the buffer when the request is in the size of the maximum TLP size or when the threshold value is exceeded.Type: GrantFiled: February 24, 2021Date of Patent: December 27, 2022Assignee: Western Digital Technologies, Inc.Inventors: Amir Segev, Amir Rozen, Shay Benisty
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Publication number: 20220276962Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, wherein the command comprises a plurality of logical block addresses (LBAs), determine that one or more LBAs of the plurality of LBAs are not aligned to a transfer layer packet (TLP) boundary, determine whether the one or more LBAs that are not aligned to a TLP boundary has a head that is unaligned that matches a previously stored tail that is unaligned, and merge and transfer the head that is unaligned with a previously stored tail that is unaligned when the head that is unaligned matches the previously stored tail that is unaligned.Type: ApplicationFiled: May 18, 2022Publication date: September 1, 2022Applicant: Western Digital Technologies, Inc.Inventors: Amir SEGEV, Amir ROZEN, Shay BENISTY
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Publication number: 20220164291Abstract: The present disclosure generally relates to effective transport layer packet (TLP) utilization. When the controller of the data storage device generates a request for transferring data to or from the storage device, the request is stored in a merging buffer. The merging buffer may include previously generated requests, where the previously generated requests and the new requests are merged. A timeout counter is initialized for the requests stored in the merging buffer. The timeout counter has a configurable threshold value that corresponds to a weight value, adjusted for latency or bandwidth considerations. When the merged request is greater than the maximum TLP size, the merged request is partitioned, where at least one partition is in the size of the maximum TLP size. The request is sent from the buffer when the request is in the size of the maximum TLP size or when the threshold value is exceeded.Type: ApplicationFiled: February 24, 2021Publication date: May 26, 2022Inventors: Amir SEGEV, Amir ROZEN, Shay BENISTY
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Publication number: 20210397511Abstract: A method and apparatus for allocation of back-end (BE) logic resources between NVM sets. When a controller detects that an NVM set is in an idle state, it deallocates the BE logic from the originally assigned NVM set and provides the BE logic resource to another NVM set. An NVM set controller matrix maps interconnections between the BE logic resource and the new NVM set to enable use of the BE logic resource and the new NVM set. When a new command arrives for the originally assigned NVM set, the BE logic resources is re-allocated to the originally assigned NVM set.Type: ApplicationFiled: June 19, 2020Publication date: December 23, 2021Inventors: Amir ROZEN, Shay BENISTY, Vitali LINKOVSKY
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Patent number: 11204833Abstract: A method and apparatus for allocation of back-end (BE) logic resources between NVM sets. When a controller detects that an NVM set is in an idle state, it deallocates the BE logic from the originally assigned NVM set and provides the BE logic resource to another NVM set. An NVM set controller matrix maps interconnections between the BE logic resource and the new NVM set to enable use of the BE logic resource and the new NVM set. When a new command arrives for the originally assigned NVM set, the BE logic resources is re-allocated to the originally assigned NVM set.Type: GrantFiled: June 19, 2020Date of Patent: December 21, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Amir Rozen, Shay Benisty, Vitali Linkovsky
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Patent number: 10727965Abstract: A system and method for time stamp synchronization are disclosed. In one embodiment, first and second devices are provided. The second device receives a first time stamp of the first device, wherein the first time stamp was generated in response to a time stamp synchronization event common to the first and second devices; generates a second time stamp of the second device in response to the time stamp synchronization event, wherein the first and second time stamps are in different time domains; and correlates the first and second time stamps, wherein correlating the first and second time stamps provide a relationship between the time domains because the first and second time stamps were both generated with respect to the same time stamp synchronization event common to the first and second devices.Type: GrantFiled: November 21, 2017Date of Patent: July 28, 2020Assignee: Western Digital Technologies, Inc.Inventors: David Brief, Tomer Spector, Amir Rozen
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Patent number: 10387226Abstract: A system on a chip or storage device has a dynamic process for handling system events that are transmitted at varying transmission rates. This dynamic process is a hybrid mode of operation that tailors the use of time stamp information according to the dynamic flow of events that are submitted in the system. Relative time stamps can be used along with explicit time stamps. Periodic wrap around events which use relative time stamps based on the periodic wrap events may be suppressed when there were no events between consecutive wrap around events. When an asynchronous event occurs during the suppression, the event is identified with a high precision time stamp (HPTS) rather than a relative time stamp. The periodic wrap around events can be re-initiated after the HPTS event is stamped.Type: GrantFiled: November 13, 2017Date of Patent: August 20, 2019Assignee: Western Digital Technologies, Inc.Inventors: David Brief, Arseniy Aharonov, Amir Rozen, Asaf Gueta
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Publication number: 20190158203Abstract: A system and method for time stamp synchronization are disclosed. In one embodiment, first and second devices are provided. The second device receives a first time stamp of the first device, wherein the first time stamp was generated in response to a time stamp synchronization event common to the first and second devices; generates a second time stamp of the second device in response to the time stamp synchronization event, wherein the first and second time stamps are in different time domains; and correlates the first and second time stamps, wherein correlating the first and second time stamps provide a relationship between the time domains because the first and second time stamps were both generated with respect to the same time stamp synchronization event common to the first and second devices.Type: ApplicationFiled: November 21, 2017Publication date: May 23, 2019Applicant: Western Digital Technologies, Inc.Inventors: David Brief, Tomer Spector, Amir Rozen
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Publication number: 20190146856Abstract: A system on a chip or storage device has a dynamic process for handling system events that are transmitted at varying transmission rates. This dynamic process is a hybrid mode of operation that tailors the use of time stamp information according to the dynamic flow of events that are submitted in the system. Relative time stamps can be used along with explicit time stamps. Periodic wrap around events which use relative time stamps based on the periodic wrap events may be suppressed when there were no events between consecutive wrap around events. When an asynchronous event occurs during the suppression, the event is identified with a high precision time stamp (HPTS) rather than a relative time stamp. The periodic wrap around events can be re-initiated after the HPTS event is stamped.Type: ApplicationFiled: November 13, 2017Publication date: May 16, 2019Applicant: Western Digital Technologies, Inc.Inventors: David Brief, Arseniy Aharonov, Amir Rozen, Asaf Gueta
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Publication number: 20170116117Abstract: A data storage device includes a non-volatile memory device and a controller including a first memory. The first memory stores data indicating a metric. The controller is configured to receive data corresponding to a portion of a second memory of an access device. Multiple portions of the second memory are allocated for use by the controller, and the multiple portions are indicated by a plurality of descriptors that includes sizes of the multiple portions. The controller is also configured to determine a subset of the plurality of descriptors based on the metric and to determine a physical address corresponding to the portion of the second memory based on a descriptor of the subset of descriptors.Type: ApplicationFiled: October 26, 2015Publication date: April 27, 2017Inventors: Amir Rozen, Shay Benisty