Patents by Inventor Amir Shaharabany

Amir Shaharabany has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960394
    Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To Utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Shaharabany, Shay Vaza
  • Patent number: 11960395
    Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Shaharabany, Shay Vaza
  • Patent number: 11782648
    Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: October 10, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Eliad Adi Klein
  • Publication number: 20230079698
    Abstract: Aspects of the present disclosure generally relate to data storage devices, systems, and related methods that determine writing fragmentation levels of memory devices, such as memory devices of solid-state drives (SSDs). In one aspect, a controller of a data storage device is configured to determine a plurality of valid counts of a plurality of blocks of one or more memory devices, and arrange the plurality of valid counts of the plurality of blocks into a plurality of valid count groupings. The plurality of valid counts is arranged into a histogram having the plurality of block counts and the plurality of valid count groupings. In one aspect, the controller is configured to multiply the plurality of block counts by a plurality of assigned weights to determine a plurality of writing fragmentation values. In one aspect, the controller is configured to determine a writing fragmentation level.
    Type: Application
    Filed: September 16, 2021
    Publication date: March 16, 2023
    Inventors: Amir SHAHARABANY, Adi FOGEL, Nadav SOBER
  • Patent number: 11537320
    Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a write command from the host that is recognized by the storage system as a read host memory command; in response to receiving the write command, send an identification of a location in the host memory to the host; and receive, from the host, data that is stored in the location in the host memory. Other embodiments are provided.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Eliad Adi Klein
  • Publication number: 20220358035
    Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To Utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SHAHARABANY, Shay VAZA
  • Publication number: 20220358036
    Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SHAHARABANY, Shay VAZA
  • Patent number: 11467743
    Abstract: The present disclosure describes technologies and techniques for use by a data storage controller—such as a controller for use with a NAND or other non-volatile memory (NVM)—to provide a user-expandable memory space. In examples described herein, a customer may choose to purchase access to only a portion of the total available memory space of a consumer device, such as a smartphone. Later, the customer may expand the user-accessible memory space. In one example, the customer submits suitable payment via a communication network to a centralized authorization server, which returns an unlock key. Components within the data storage controller of the consumer device then use the key to unlock additional memory space within the device. In this manner, if the initial amount of memory the consumer paid for becomes full, the consumer may conveniently expand the amount of user-accessible memory.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: October 11, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Liran Sharoni, Amir Shaharabany
  • Patent number: 11429522
    Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: August 30, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Shaharabany, Shay Vaza
  • Publication number: 20220236919
    Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Eliad Adi Klein
  • Patent number: 11327684
    Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: May 10, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Eliad Adi Klein
  • Publication number: 20220114088
    Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.
    Type: Application
    Filed: February 23, 2021
    Publication date: April 14, 2022
    Inventors: Amir SHAHARABANY, Shay VAZA
  • Patent number: 11199997
    Abstract: In one non-limiting embodiment, a method is disclosed for performing a storage device operation on a die is provide having steps of choosing a storage device operation to perform, estimating which die is related to the storage device operation chosen to be performed and performing the storage device operation at the die based on the estimating.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: December 14, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amir Shaharabany, Hadas Oshinsky
  • Publication number: 20210357148
    Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.
    Type: Application
    Filed: May 14, 2020
    Publication date: November 18, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Eliad Adi Klein
  • Publication number: 20210240389
    Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a write command from the host that is recognized by the storage system as a read host memory command; in response to receiving the write command, send an identification of a location in the host memory to the host; and receive, from the host, data that is stored in the location in the host memory. Other embodiments are provided.
    Type: Application
    Filed: February 3, 2020
    Publication date: August 5, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Eliad Adi Klein
  • Publication number: 20210223972
    Abstract: The present disclosure describes technologies and techniques for use by a data storage controller—such as a controller for use with a NAND or other non-volatile memory (NVM)—to provide a user-expandable memory space. In examples described herein, a customer may choose to purchase access to only a portion of the total available memory space of a consumer device, such as a smartphone. Later, the customer may expand the user-accessible memory space. In one example, the customer submits suitable payment via a communication network to a centralized authorization server, which returns an unlock key. Components within the data storage controller of the consumer device then use the key to unlock additional memory space within the device. In this manner, if the initial amount of memory the consumer paid for becomes full, the consumer may conveniently expand the amount of user-accessible memory.
    Type: Application
    Filed: April 1, 2021
    Publication date: July 22, 2021
    Inventors: Liran Sharoni, Amir Shaharabany
  • Patent number: 10983715
    Abstract: The present disclosure describes technologies and techniques for use by a data storage controller—such as a controller for use with a NAND or other non-volatile memory (NVM)—to provide a user-expandable memory space. In examples described herein, a customer may choose to purchase access to only a portion of the total available memory space of a consumer device, such as a smartphone. Later, the customer may expand the user-accessible memory space. In one example, the customer submits suitable payment via a communication network to a centralized authorization server, which returns an unlock key. Components within the data storage controller of the consumer device then use the key to unlock additional memory space within the device. In this manner, if the initial amount of memory the consumer paid for becomes full, the consumer may conveniently expand the amount of user-accessible memory.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: April 20, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Liran Sharoni, Amir Shaharabany
  • Patent number: 10901620
    Abstract: A storage system and method for thin provisioning are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to provide a logical exported capacity of the memory to a host, wherein the logical exported capacity is greater than an actual storage capacity of the memory; receive a command from the host to write data to a logical address; determine whether there is available actual storage capacity in the memory to write the data; and write the data to a physical address in memory that corresponds to the logical address only if it is determined that there is available actual storage capacity in the memory to write the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Shaharabany, Michael Zaidman, Rotem Sela, Hadas Oshinsky
  • Patent number: 10802734
    Abstract: The disclosure relates to optimizing a mount process at a data storage device. The storage device communicates with a host using a mount process and mounts a master table, the master table caching translation table pointers associated with a boot partition. The storage device then sends a ready signal to the host indicating that the storage device is ready to receive a boot partition read command from the host. The storage device suspends the mount process for a window of time to receive the boot partition read command and executes the boot partition read command if the boot partition read command is received during the window of time. Accordingly, by caching boot partition pointers in the master table, the mount time of the boot partition is shortened to allow the storage device to send the ready signal earlier and provide the host with earlier access to the boot partition.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 13, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Shaharabany, Ivo Faldini, Arseniy Aharonov, Miki Sapir
  • Patent number: 10725792
    Abstract: A memory device is embedded in (or connected to) a host device. The memory device includes a first boot partition and a second boot partition. The first boot partition stores first boot data. The second boot partition stores second boot data. The memory device includes a pointer that points to either the first boot partition or the second boot partition. The memory device transfers the first boot data from the first boot partition in response to receiving a boot signal from the host and the pointer pointing to the first boot partition. The host attempts to boot using the first boot data. If the host does not boot successfully from the first boot data then the host is booted from second boot data transferred from the memory device without the host requesting that the pointer switch to pointing at the second boot data.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Miki Sapir