Abstract: A method and apparatus for process control in a lithographic process are described. Metrology may be performed on a substrate either before or after performing a lithographic patterning process on the substrate. One or more correctables to the lithographic patterning process may be generated based on the metrology. The lithographic patterning process performed on the substrate (or a subsequent substrate) may be adjusted with the correctables.

Abstract: A method for automatic process control (APC) performance monitoring may include, but is not limited to: computing one or more APC performance indicators for one or more production lots of semiconductor devices; and displaying a mapping of the one or more APC performance indicators to the one or more production lots of semiconductor devices.

Abstract: Disclosed are apparatus and methods for optimizing a metrology tool, such as an optical or scanning electron microscope so that minimum human intervention is achievable during the optimization. In general, a set of specifications and an initial input data are initially provided for a particular target. The specifications provide limits for characteristics of images that are to be measured by the metrology tool. The metrology tool is then automatically optimized for measuring the particular target so as to meet one or more of the provided specifications without further significant human intervention with respect to the metrology tool. In one aspect, the input data provided prior to the automated optimization procedure includes a plurality of target locations and a synthetic image of the particular target.

Abstract: Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.

Abstract: Computer-implemented methods, carrier media, and systems for creating a metrology target structure design for a reticle layout are provided. One computer-implemented method for creating a metrology target structure design for a reticle layout includes simulating how one or more initial metrology target structures will be formed on a wafer based on one or more fabrication processes that will be used to form a metrology target structure on the wafer and one or more initial metrology target structure designs. The method also includes creating the metrology target structure design based on results of the simulating step.

Abstract: A combined metrology mark, a system, and a method for calculating alignment on a semiconductor circuit are disclosed. The combined metrology mark may include a mask misregistration structure and a wafer overlay mark structure.

Abstract: A method for optimizing alignment performance in a fleet of exposure systems involves characterizing each exposure system in a fleet of exposure systems to generate a set of distinctive distortion profiles associated with each exposure system. The set of distinctive distortion profiles are stored in a database. A wafer having reference pattern formed thereon is provided for further pattern fabrication and an exposure system is selected from the fleet to fabricate a next layer on the wafer. Linear and higher order parameters of the selected exposure system are adjusted using the distinctive distortion profiles to model the distortion of the reference pattern. Once the exposure system is adjusted, it is used to form a lithographic pattern on the wafer.

Abstract: Disclosed are semiconductor targets for measuring with a metrology tool having at least two incident beam modules and techniques for measuring the same. In one embodiment, the target includes an overlay target and a critical dimension (CD) target in the form of periodic features, and the overlay and CD targets are spaced apart by a distance that substantially matches a bore distance between two of the incident beam modules of the metrology tool. In another embodiment, the target includes two overlay targets in the form of periodic features and that are spaced apart by a distance that substantially matches a bore distance between two of the incident beam modules of the metrology tool. In another embodiment, the target includes two CD targets in the form of periodic features and that are spaced apart by a distance that substantially matches a bore distance between two of the incident beam modules of the metrology tool.

Abstract: A method and apparatus for process control in a lithographic process are described. Metrology may be performed on a substrate either before or after performing a lithographic patterning process on the substrate. One or more correctables to the lithographic patterning process may be generated based on the metrology. The lithographic patterning process performed on the substrate (or a subsequent substrate) may be adjusted with the correctables.

Abstract: Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one lot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.

Abstract: Disclosed are apparatus and methods for optimizing a metrology tool, such as an optical or scanning electron microscope so that minimum human intervention is achievable during the optimization. In general, a set of specifications and an initial input data are initially provided for a particular target. The specifications provide limits for characteristics of images that are to be measured by the metrology tool. The metrology tool is then automatically optimized for measuring the particular target so as to meet one or more of the provided specifications without further significant human intervention with respect to the metrology tool. In one aspect, the input data provided prior to the automated optimization procedure includes a plurality of target locations and a synthetic image of the particular target.

Abstract: A method for optimizing alignment performance in a fleet of exposure systems involves characterizing each exposure system in a fleet of exposure systems to generate a set of distinctive distortion profiles associated with each exposure system. The set of distinctive distortion profiles are stored in a database. A wafer having reference pattern formed thereon is provided for further pattern fabrication and an exposure system is selected from the fleet to fabricate a next layer on the wafer. Linear and higher order parameters of the selected exposure system are adjusted using the distinctive distortion profiles to model the distortion of the reference pattern. Once the exposure system is adjusted, it is used to form a lithographic pattern on the wafer.

Abstract: Computer-implemented methods, carrier media, and systems for creating a metrology target structure design for a reticle layout are provided. One computer-implemented method for creating a metrology target structure design for a reticle layout includes simulating how one or more initial metrology target structures will be formed on a wafer based on one or more fabrication processes that will be used to form a metrology target structure on the wafer and one or more initial metrology target structure designs. The method also includes creating the metrology target structure design based on results of the simulating step.

Abstract: Apparatus for cleaning a surface of a substrate includes a cooling device, which is adapted to cool a region of the substrate in a vicinity of a particle on the surface, so as to cause a fluid in contact with the surface to form a frozen film in the vicinity of the particle. A radiation source is adapted to direct a beam of energy toward the surface so as to cause vaporization of the film due to absorption of the beam in the film, thereby facilitating removal of the particle from the surface.

Abstract: Apparatus for cleaning a surface of a substrate includes a cooling device, which is adapted to cool a region of the substrate in a vicinity of a particle on the surface, so as to cause a fluid in contact with the surface to form a frozen film in the vicinity of the particle. A radiation source is adapted to direct a beam of energy toward the surface so as to cause vaporization of the film due to absorption of the beam in the film, thereby facilitating removal of the particle from the surface.