Abstract: The state nodes in a sequential digital circuit are identified by identifying the minimal combinatorial feedback loops that are present in the digital circuit. Each minimal combinatorial feedback loop has at least one driver node, and one driver node from each minimal combinatorial feedback loop is assigned to be the state node for the loop.

Abstract: A method is provided for simulating a sequential digital circuit module given a set of input conditions and a current state for the circuit. The method comprises initiating all state nodes of the circuit module to logic values stored in the current state, initializing all sequential submodules of the circuit module to the states stored in the current state, simulating the circuit module after initialization, and after completion of the simulation step, reporting the output logic values and associated delays and storing the logic values of the state nodes and the states of the sequential modules in the next state in the circuit module, multiple value changes in the state nodes of the circuit module being recorded on the next state.

Abstract: An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and the resulting output values and delays have been evaluated, another instance of the same module need not be re-simulated when it has the same input combination as the prior circuit module instance. The results computed earlier for the earlier circuit module instance can be re-used for the current circuit module instance.

Abstract: Sequential digital integrated circuits have stable state nodes that are capable of retaining their state (logic value) even in the absence of any input directly driving these points. However, in addition to stable state nodes, some custom-designed digital circuits have so-called transient state nodes. A transient state node is defined as node that can directly affect the value of a stable state node and is combinatorially driven by inputs of the circuit, but the transition delay from at least one input to the node is greater than a predefined threshold value. Identifying such transient state nodes, along with the stable state nodes, is critical for the efficient simulation of custom digital circuits by a hierarchical device level digital simulator. A method is provided herein for identifying transient state nodes in a digital circuit, given the circuit's netlist and the identity of the stable state nodes in the circuit.

Abstract: The state nodes in a sequential digital circuit are identified by identifying the minimal combinatorial feedback loops that are present in the digital circuit. Each minimal combinatorial feedback loop has at least one driver node, and one driver node from each minimal combinatorial feedback loop is assigned to be the state node for the loop.